JAJSO91 December   2023 TPS55289-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VCC Power Supply
      2. 6.3.2  EXTVCC Power Supply
      3. 6.3.3  I2C Address Selection
      4. 6.3.4  Input Undervoltage Lockout
      5. 6.3.5  Enable and Programmable UVLO
      6. 6.3.6  Soft Start
      7. 6.3.7  Shutdown and Load Discharge
      8. 6.3.8  Switching Frequency
      9. 6.3.9  Switching Frequency Dithering
      10. 6.3.10 Inductor Current Limit
      11. 6.3.11 Internal Charge Path
      12. 6.3.12 Output Voltage Setting
      13. 6.3.13 Output Current Monitoring and Cable Voltage Droop Compensation
      14. 6.3.14 Output Current Limit
      15. 6.3.15 Overvoltage Protection
      16. 6.3.16 Output Short Circuit Protection
      17. 6.3.17 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Power Save Mode
    5. 6.5 Programming
      1. 6.5.1 Data Validity
      2. 6.5.2 START and STOP Conditions
      3. 6.5.3 Byte Format
      4. 6.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 6.5.5 target Address and Data Direction Bit
      6. 6.5.6 Single Read and Write
      7. 6.5.7 Multi-Read and Multi-Write
  8. 7 Register Maps
    1. 7.1 REF Register (Address = 0h, 1h) [reset = 10100100b, 00000001b]
    2. 7.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100b]
    3. 7.3 VOUT_SR Register (Address = 3h) [reset = 00000001b]
    4. 7.4 VOUT_FS Register (Address = 4h) [reset = 00000011b]
    5. 7.5 CDC Register (Address = 5h) [reset = 11100000b]
    6. 7.6 MODE Register (Address = 6h) [reset = 00100000b]
    7. 7.7 STATUS Register (Address = 7h) [reset = 00000011b]
    8. 7.8 Register Summary
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Output Voltage Setting
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Output Current Limit
        7. 8.2.2.7 Loop Stability
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.12 Output Voltage Setting

There are two ways to set the output voltage: changing the feedback ratio and changing the reference voltage. The TPS55289-Q1 has a 11-bit DAC to program the reference voltage from 45mV to 1.2V. The TPS55289-Q1 also can select an internal feedback resistor divider or an external resistor divider by setting the FB bit in register 04h. When the FB bit is set to 0, the output voltage feedback ratio is set in internal register 04h. When the FB bit is set to 1, the output voltage feedback ratio is set by an external resistor divider.

When using internal output voltage feedback settings, there are four feedback ratios programmable by writing the INTFB[1:0] bits of register 04h. With this function, the TPS55289-Q1 can limit the maximum output voltage to different values. In addition, the minimum step of the output voltage change is also programmed to 10mV, 7.5mV, 5mV, and 2.5mV, accordingly.

When using an external output voltage feedback resistor divider as shown in Figure 6-5, use Equation 5 to calculate the output voltage with the reference voltage at the FB/INT pin.

Equation 5. GUID-D091304F-05F7-492D-B99F-9E0C5CDA6852-low.gif
GUID-F3813D3F-7F4C-4CA9-BE4C-50277D1B39C0-low.gif Figure 6-5 Output Voltage Setting by External Resistor Divider

TI recommends using 100kΩ for the up resistor RFB_UP. The reference voltage VREF at the FB/INT pin is programmable from 45mV to 1.2V by writing a 11-bit data into register 00h and 01h.