JAJS453E November   2007  – April 2019 TPS61165

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Thermal Information
    4. 7.4 Electrical Characteristics
    5. 7.5 Timing Requirements
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Soft Start-Up
      2. 8.3.2 Open LED Protection
      3. 8.3.3 Undervoltage Lockout
      4. 8.3.4 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Maximum Output Current
      2. 9.1.2 Inductor Selection
      3. 9.1.3 Schottky Diode Selection
      4. 9.1.4 Compensation Capacitor Selection
      5. 9.1.5 Input and Output Capacitor Selection
    2. 9.2 Typical Applications
      1. 9.2.1 TPS61165 Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 LED Brightness Dimming Mode Selection
          2. 9.2.1.2.2 PWM Brightness Dimming
          3. 9.2.1.2.3 Digital One-Wire Brightness Dimming
          4. 9.2.1.2.4 EasyScale: One-Wire Digital Dimming
          5. 9.2.1.2.5 Current Program
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Additional Application Circuits
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.3 Thermal Considerations

The maximum device junction temperature must be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation of the TPS61165. Calculate the maximum allowable dissipation, PD(max), and keep the actual dissipation less than or equal to PD(max). The maximum-power-dissipation limit is determined using Equation 8:

Equation 8. TPS61165 q8_pdm_lvs790.gif

where

  • TA is the maximum ambient temperature for the application
  • RθJA is the thermal resistance junction-to-ambient given in Thermal Information

The TPS61165 comes in a thermally enhanced QFN package. This package includes a thermal pad that improves the thermal capabilities of the package. The RθJA of the QFN package greatly depends on the PCB layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using thermal vias underneath the thermal pad as illustrated in the layout example. Also see the QFN/SON PCB Attachment application report (SLUA271).