JAJSCE8B July   2016  – October 2018 TPS61230A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
      2.      効率
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Startup
      2. 8.3.2 Enable and Disable
      3. 8.3.3 Under-Voltage Lockout (UVLO)
      4. 8.3.4 Current Limit Operation
      5. 8.3.5 Over Voltage Protection
      6. 8.3.6 Load Disconnect
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM Mode
      2. 8.4.2 PFM Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS61230A 2.5-V to 4.5-V Input, 5-V Output Converter
        1. 9.2.1.1 TPS61230A 5-V Output Design Requirements
        2. 9.2.1.2 TPS61230A 5-V Detailed Design Procedure
          1. 9.2.1.2.1 Programming The Output Voltage
          2. 9.2.1.2.2 Inductor and Capacitor Selection
            1. 9.2.1.2.2.1 Inductor Selection
            2. 9.2.1.2.2.2 Output Capacitor Selection
            3. 9.2.1.2.2.3 Input Capacitor Selection
          3. 9.2.1.2.3 Loop Stability, Feed Forward Capacitor
        3. 9.2.1.3 TPS61230A 5-V Output Application Performance Plots
      2. 9.2.2 Systems Example - TPS61230A with Feed Forward Capacitor for Best Transient Response
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1 Overview

The TPS61230A is a high efficiency synchronous boost converter with integrating the 21-mΩ low side FET and 18-mΩ high side FET. The device could deliver up to 12-W output power with 5.5-V maximum output voltage from single cell Li-Iron battery. TPS61230A uses a quasi constant on-time valley current mode which provides an excellent transient response. The TPS61230xA typically operates at a quasi-constant 1.15-MHz frequency pulse width modulation (PWM) at the moderate to heavy load currents, allows the use of small inductor and capacitors to achieve a compact solution size.

During the PWM operation, a simple circuit predicts the required on time (with the VIN / VOUT ratio) of the ow-side FET. At the beginning of each switching cycle, the low-side FET turns on and the inductor current ramps up to the peak current determined by the on-time and the inductance. Once the on-timer expires, the high-side FET turns on and the inductor current decays to a preset valley current threshold determined by the Error Amplifier’s output. The switching cycle repeats again by calculating the on time and activating the low-side FET.

At the light load currents, TPS61230A operates in Power Save Mode with pulse frequency modulation (PFM) and improves the efficiency under the light load.

Internal soft-start and loop compensation simplifies the design process and minimizes the number of external components.