JAJSI60 November   2019 TPS61391

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Recommended Operating Conditions
    2. 6.2 Absolute Maximum Ratings
    3. 6.3 ESD Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout
      2. 7.3.2 Enable and Disable
      3. 7.3.3 Current Mirror
      4. 7.3.4 High Optical Power Protection
    4. 7.4 Device Functional Mode
      1. 7.4.1 PFM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirement
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Rectifier Diode
        2. 8.2.2.2  Selecting the Inductor
        3. 8.2.2.3  Selecting Output Capacitor
        4. 8.2.2.4  Selecting Filter Resistor and Capacitor
        5. 8.2.2.5  Setting the Output Voltage
        6. 8.2.2.6  Selecting Capacitor for CAP pin
        7. 8.2.2.7  Selecting Capacitor for AVCC pin
        8. 8.2.2.8  Selecting Capacitor for APD pin
        9. 8.2.2.9  Selecting the Resistors of MON1 or MON2
        10. 8.2.2.10 Selecting the Capacitors of MON1 or MON2
        11. 8.2.2.11 Selecting the Short Current Limit
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.4 High Optical Power Protection

There is an additional FET in series of power path connecting with the APD. When the current flowing through the APD exceeds the short protection threshold (set by connecting the resistor from ISHORT to GND), the on resistance of the FET becomes larger to clamp the current within the protection threshold by lowering the APD bias voltage. It takes typically 0.5 µs for the FET to respond in case of high optical power occuring.

When the high optical power condition releases, the TPS61391 recovers automatically back to the normal operation mode.