JAJSEC9D May   2014  – January 2018 TPS6213013A-Q1 , TPS62130A-Q1 , TPS62133A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Pulse Width Modulation (PWM) Operation
      2. 9.3.2  Power Save Mode Operation
      3. 9.3.3  100% Duty-Cycle Operation
      4. 9.3.4  Enable / Shutdown (EN)
      5. 9.3.5  Soft Start / Tracking (SS/TR)
      6. 9.3.6  Current Limit And Short Circuit Protection
      7. 9.3.7  Power Good (PG)
      8. 9.3.8  Pin-Selectable Output Voltage (DEF)
      9. 9.3.9  Frequency Selection (FSW)
      10. 9.3.10 Under Voltage Lockout (UVLO)
      11. 9.3.11 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation Above TJ=125°C
      2. 9.4.2 Operation with VIN < 3V
      3. 9.4.3 Operation with Separate EN Control
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 TPS62130A-Q1 Point-Of-Load Step Down Converter
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 10.2.1.2.2 Programming The Output Voltage
          3. 10.2.1.2.3 External Component Selection
          4. 10.2.1.2.4 Inductor Selection
          5. 10.2.1.2.5 Output Capacitor
          6. 10.2.1.2.6 Input Capacitor
          7. 10.2.1.2.7 Soft Start Capacitor
          8. 10.2.1.2.8 Tracking Function
          9. 10.2.1.2.9 Output Filter And Loop Stability
        3. 10.2.1.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Regulated Power LED Supply
      2. 10.3.2 Inverting Power Supply
      3. 10.3.3 Active Output Discharge
      4. 10.3.4 Various Output Voltages
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGT|16
サーマルパッド・メカニカル・データ
発注情報

12.1 Layout Guidelines

A proper layout is critical for the operation of a switched mode power supply, even more at high switching frequencies. Therefore the PCB layout of the TPS6213xA-Q1 demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation and noise sensitivity. The layout also influences the thermal performance of the solution by its power dissipation capabilities.

See Figure 55 for the recommended layout of the TPS62130A-Q1, which is designed for common external ground connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to the VOUT potential at the output capacitor.

Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.

Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (e.g. SW). As they carry information about the output voltage, they should be connected as close as possible to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the AGND pin.

The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve appropriate power dissipation.

The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the EVM Gerber data are available for download here, SLVC394.