JAJSBL0E November   2011  – May 2017 TPS62170 , TPS62171 , TPS62172 , TPS62173

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Voltage Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable and Shutdown (EN)
      2. 8.3.2 Current Limit and Short Circuit Protection
      3. 8.3.3 Power Good (PG)
      4. 8.3.4 Undervoltage Lockout (UVLO)
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft Start
      2. 8.4.2 Pulse Width Modulation (PWM) Operation
      3. 8.4.3 Power Save Mode Operation
      4. 8.4.4 100% Duty-Cycle Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design with WEBENCH® Tools
        2. 9.2.2.2 Programming the Output Voltage
        3. 9.2.2.3 External Component Selection
          1. 9.2.2.3.1 Inductor Selection
        4. 9.2.2.4 Capacitor Selection
          1. 9.2.2.4.1 Output Capacitor
          2. 9.2.2.4.2 Input Capacitor
        5. 9.2.2.5 Output Filter and Loop Stability
        6. 9.2.2.6 TPS6216x Components List
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Inverting Power Supply
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
TPS62170 TPS62171 TPS62172 TPS62173 SLVSAT8_pinout_DSG.gif

Pin Functions

PIN(1) I/O DESCRIPTION
NAME NO.
PGND 1 — Power ground
VIN 2 IN Supply voltage
EN 3 IN Enable input (High = enabled, Low = disabled)
AGND 4 — Analog ground
FB 5 IN Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended to connect FB to AGND on fixed output voltage versions for improved thermal performance.
VOS 6 IN Output voltage sense pin and connection for the control loop circuitry.
SW 7 OUT Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and output capacitor.
PG 8 OUT Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain (requires pull-up resistor; goes high impedance, when device is switched off)
Exposed Thermal Pad — Must be connected to AGND. Must be soldered to achieve appropriate power dissipation and mechanical reliability.
(1) For more information about connecting pins, see Detailed Description and Application Information sections.