SLVSA67F February   2010  – April 2020 TPS62400-Q1 , TPS62402-Q1 , TPS62404-Q1 , TPS62405-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      TPS62402-Q1 Efficiency versus Output Current, VOUT1 and VOUT2
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Converter 1
      2. 9.1.2 Converter 2
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable
      2. 9.3.2 DEF_1 Pin Function
      3. 9.3.3 180° Out-of-Phase Operation
      4. 9.3.4 Short-Circuit Protection
      5. 9.3.5 Thermal Shutdown
      6. 9.3.6 EasyScale Interface: One-Pin Serial Interface for Dynamic Output-Voltage Adjustment
        1. 9.3.6.1 General
        2. 9.3.6.2 Protocol
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Save Mode
        1. 9.4.1.1 Dynamic Voltage Positioning
        2. 9.4.1.2 Soft Start
        3. 9.4.1.3 100% Duty-Cycle Low-Dropout Operation
        4. 9.4.1.4 Undervoltage Lockout
      2. 9.4.2 Mode Selection
    5. 9.5 Programming
      1. 9.5.1 Addressable Registers
        1. 9.5.1.1 Bit Decoding
        2. 9.5.1.2 Acknowledge
        3. 9.5.1.3 Mode Selection
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Output Voltage Setting
          1. 10.2.2.1.1 Converter 1 Adjustable Default Output-Voltage Setting: TPS62400-Q1
          2. 10.2.2.1.2 Converter 1 Fixed Default Output-Voltage Setting (TPS62402-Q1, TPS62404-Q1, and TPS62405-Q1)
          3. 10.2.2.1.3 Converter 2 Adjustable Default Output-Voltage Setting (TPS62400-Q1):
          4. 10.2.2.1.4 Converter 2 Fixed Default Output-Voltage Setting
        2. 10.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 10.2.2.2.1 Inductor Selection
          2. 10.2.2.2.2 Output-Capacitor Selection
          3. 10.2.2.2.3 Input Capacitor Selection
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.5.1.3 Mode Selection

Use of the MODE/DATA pin for two functions, interface and mode selection, necessitates a determination of when to decode the bit stream or to change the operation mode.

The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level. The device also stays in forced PWM mode during the entire protocol reception time.

With a falling edge on the MODE/DATA pin, the device starts bit decoding. If the MODE/DATA pin stays low for at least ttimeout, the device gets an internal time-out and enables power-save-mode operation.

The device ignores a protocol sent within this time because the first interpretation of a falling edge for the mode change is at the start of the first bit. In this case, TI recommends sending the protocol first, and then changing to power-save mode at the end of the protocol.

TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1 reg_ovr_vw_slvsa67.gifFigure 9. EasyScale Protocol Overview

Table 3. EasyScale Bit Description

BYTE BIT NUMBER NAME TRANSMISSION DIRECTION DESCRIPTION
Device address byte 7 DA7 IN 0 MSB device address
6 DA6 IN 1
5 DA5 IN 0
4 DA4 IN 0
4E hex 3 DA3 IN 1
2 DA2 IN 1
1 DA1 IN 1
0 DA0 IN 0 LSB device address
Data byte 7 (MSB) RFA IN Request for acknowledge; if high, the device applies an acknowledge condition.
6 A1 Address bit 1
5 A0 Address bit 0
4 D4 Data bit 4
3 D3 Data bit 3
2 D2 Data bit 2
1 D1 Data bit 1
0 (LSB) D0 Data bit 0
ACK OUT Acknowledge condition active 0, the device applies this condition only in the case of a set RFA bit. Open-drain output, the host must pull the line high with a pullup resistor.
One can only use this feature if the master has an open-drain output stage. In case of a push-pull output stage, do not request an acknowledge condition.
TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1 es_proto_slvsa67.gifFigure 10. EasyScale Protocol Without Acknowledge
TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1 es_proto2_slvsa67.gifFigure 11. EasyScale Protocol Including Acknowledge
TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1 bit_coding_slvsa67.gifFigure 12. EasyScale – Bit Coding
TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1 mode_pin_slvsa67.gifFigure 13. MODE/DATA PIN: Mode Selection
TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1 pwr_svr_slvsa67.gifFigure 14. MODE/DATA Pin: Power-Save-Mode and Interface Communication

Table 4. Selectable Output Voltages for Converter 1,
With Pin DEF_1 as Digital Input (TPS62402-Q1)

TPS62402-Q1 OUTPUT
VOLTAGE [V]
REGISTER REG_DEF_1_LOW		 TPS62402-Q1 OUTPUT
VOLTAGE [V]
REGISTER REG_DEF_1_HIGH		 D4 D3 D2 D1 D0
0 0.8 0.9 0 0 0 0 0
1 0.825 0.925 0 0 0 0 1
2 0.85 0.95 0 0 0 1 0
3 0.875 0.975 0 0 0 1 1
4 0.9 1.0 0 0 1 0 0
5 0.925 1.025 0 0 1 0 1
6 0.95 1.050 0 0 1 1 0
7 0.975 1.075 0 0 1 1 1
8 1.0 1.1 0 1 0 0 0
9 1.025 1.125 0 1 0 0 1
10 1.050 1.150 0 1 0 1 0
11 1.075 1.175 0 1 0 1 1
12 1.1 1.2 0 1 1 0 0
13 1.125 1.225 0 1 1 0 1
14 1.150 1.25 0 1 1 1 0
15 1.175 1.275 0 1 1 1 1
16 1.2 (default TPS62402-Q1)
1.215 (default TPS62405-Q1) 		1.3 1 0 0 0 0
17 1.225 1.325 1 0 0 0 1
18 1.25 1.350 1 0 0 1 0
19 1.275 1.375 1 0 0 1 1
20 1.3 1.4 1 0 1 0 0
21 1.325 1.425 1 0 1 0 1
22 1.350 1.450 1 0 1 1 0
23 1.375 1.475 1 0 1 1 1
24 1.4 1.5 1 1 0 0 0
25 1.425 1.525 1 1 0 0 1
26 1.450 1.55 1 1 0 1 0
27 1.475 1.575 1 1 0 1 1
28 1.5 1.6 1 1 1 0 0
29 1.525 1.7 1 1 1 0 1
30 1.55 1.8 (default TPS62402-Q1) 1 1 1 1 0
31 1.575 (default TPS62404-Q1) 1.9 (default TPS62404-Q1)
1.925 (default TPS62405-Q1) 		1 1 1 1 1

Table 5. Selectable Output Voltages for Converter 1,
With DEF1 Pin as Analog Input (Adjustable, TPS62400-Q1)

TPS62400-Q1 OUTPUT VOLTAGE [V]
REGISTER REG_DEF_1_LOW		 D4 D3 D2 D1 D0
0 VOUT1 Adjustable with Resistor Network on DEF_1 Pin (default TPS62400-Q1) 0 0 0 0 0
0.6 V with DEF_1 connected to VOUT1 (default TPS62400-Q1)
1 0.825 0 0 0 0 1
2 0.85 0 0 0 1 0
3 0.875 0 0 0 1 1
4 0.9 0 0 1 0 0
5 0.925 0 0 1 0 1
6 0.95 0 0 1 1 0
7 0.975 0 0 1 1 1
8 1 0 1 0 0 0
9 1.025 0 1 0 0 1
10 1.05 0 1 0 1 0
11 1.075 0 1 0 1 1
12 1.1 0 1 1 0 0
13 1.125 0 1 1 0 1
14 1.15 0 1 1 1 0
15 1.175 0 1 1 1 1
16 1.2 1 0 0 0 0
17 1.225 1 0 0 0 1
18 1.25 1 0 0 1 0
19 1.275 1 0 0 1 1
20 1.3 1 0 1 0 0
21 1.325 1 0 1 0 1
22 1.35 1 0 1 1 0
23 1.375 1 0 1 1 1
24 1.4 1 1 0 0 0
25 1.425 1 1 0 0 1
26 1.45 1 1 0 1 0
27 1.475 1 1 0 1 1
28 1.5 1 1 1 0 0
29 1.525 1 1 1 0 1
30 1.55 1 1 1 1 0
31 1.575 1 1 1 1 1

Table 6. Selectable Output Voltages for Converter 2,
(ADJ2 Connected to VOUT2)

OUTPUT VOLTAGE [V]
FOR REGISTER REG_DEF_2		 D4 D3 D2 D1 D0
0 VOUT2 Adjustable with resistor network and Cff on ADJ2 pin (default TPS62400-Q1) 0 0 0 0 0
0.6 V with ADJ2 pin directly connected to VOUT2 (default TPS62400-Q1)
1 0.85 0 0 0 0 1
2 0.9 0 0 0 1 0
3 0.95 0 0 0 1 1
4 1 0 0 1 0 0
5 1.05 0 0 1 0 1
6 1.1 0 0 1 1 0
7 1.15 0 0 1 1 1
8 1.2 0 1 0 0 0
9 1.25 0 1 0 0 1
10 1.3 0 1 0 1 0
11 1.35 0 1 0 1 1
12 1.4 0 1 1 0 0
13 1.45 0 1 1 0 1
14 1.5 0 1 1 1 0
15 1.55 0 1 1 1 1
16 1.6 1 0 0 0 0
17 1.7 1 0 0 0 1
18 1.8 1 0 0 1 0
19 1.85 1 0 0 1 1
20 2 1 0 1 0 0
21 2.1 1 0 1 0 1
22 2.2 1 0 1 1 0
23 2.3 1 0 1 1 1
24 2.4 1 1 0 0 0
25 2.5 1 1 0 0 1
26 2.6 1 1 0 1 0
27 2.7 1 1 0 1 1
28 2.8 1 1 1 0 0
29 2.85 1 1 1 0 1
30 3 1 1 1 1 0
31 3.3 (default TPS62402-Q1, TPS62404-Q1)
3.35 (default TPS62405-Q1) 		1 1 1 1 1