SLVS551A December   2004  – September 2015 TPS65014

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics: Battery Charger
    7. 6.7  Dissipation Ratings
    8. 6.8  Serial Interface Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Step-Down Converters, VMAIN and VCORE
        1. 7.3.1.1 Forced PWM
        2. 7.3.1.2 Dynamic Voltage Positioning
        3. 7.3.1.3 Soft-Start
        4. 7.3.1.4 100% Duty Cycle Low Dropout Operation
        5. 7.3.1.5 Active Discharge When Disabled
        6. 7.3.1.6 Power-Good Monitoring
        7. 7.3.1.7 Overtemperature Shutdown
      2. 7.3.2 Low-Dropout Voltage Regulators
        1. 7.3.2.1 Power-Good Monitoring
        2. 7.3.2.2 Enabling and Sequencing
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Power-Up Sequencing
        1. 7.3.4.1 TPS65014 Power State Descriptions
          1. 7.3.4.1.1 State 1: No Power
          2. 7.3.4.1.2 State 2: ON
          3. 7.3.4.1.3 State 3: Low-Power Mode
          4. 7.3.4.1.4 State 4: Shutdown
      5. 7.3.5 System Reset and Control Signals
      6. 7.3.6 Vibrator Driver
      7. 7.3.7 LED2 Output
      8. 7.3.8 Interrupt Management
      9. 7.3.9 Serial Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Save Mode Operation
      2. 7.4.2 Sleep Mode
    5. 7.5 Register Maps
      1. 7.5.1  CHGSTATUS Register (offset = 01h) (reset: 00h)
      2. 7.5.2  REGSTATUS Register (offset = 02h) (reset: 00h)
      3. 7.5.3  MASK1 Register (offset = 03h) (reset: FFh)
      4. 7.5.4  MASK2 Register (offset = 04h) (reset: FFh)
      5. 7.5.5  ACKINT1 Register (offset = 05h) (reset: 00h)
      6. 7.5.6  ACKINT2 Register (offset: 06h) (reset: 00h)
      7. 7.5.7  CHGCONFIG Register (offset: 07h) (reset: 1Bh)
      8. 7.5.8  LED1_ON Register (offset: 08h) (reset: 00h)
      9. 7.5.9  LED1_PER Register (offset: 09h) (reset: 00h)
      10. 7.5.10 LED2_ON Register (offset: 0Ah) (reset: 00h)
      11. 7.5.11 LED2_PER (offset: 0Bh) (reset: 00h)
      12. 7.5.12 VDCDC1 Register (offset: 0Ch) (reset: 32h/33h)
      13. 7.5.13 VDCDC2 Register (offset: 0Dh) (reset: 60h/70h)
      14. 7.5.14 VREGS1 Register (offset: 0Eh) (reset: 88h)
      15. 7.5.15 MASK3 Register (offset: 0Fh) (reset: 00h)
      16. 7.5.16 DEFGPIO Register (offset = 10h) (reset: 00h)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection for the Main and the Core Converter
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Battery Charger
      1. 9.1.1 Autonomous Power Source Selection
      2. 9.1.2 Temperature Qualification
      3. 9.1.3 Battery Preconditioning
      4. 9.1.4 Battery Charge Current
      5. 9.1.5 Battery Voltage Regulation
      6. 9.1.6 Charge Termination and Recharge
      7. 9.1.7 PG Output
      8. 9.1.8 Thermal Considerations for Setting Charge Current
    2. 9.2 LDO1 Output Voltage Adjustment
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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発注情報

7 Detailed Description

7.1 Overview

The TPS65014 has a highly integrated and flexible Li-Ion linear charger and system power management. It offers an integrated USB port and AC-adapter supply management with autonomous power-source selection, power FET and current sensor, high accuracy current and voltage regulation, charge status, and charge termination.

The TPS65014 charger automatically selects the USB port or the AC adapter as the power source for the system. In the USB configuration, the host can increase the charge current from the default value of maximum 100 mA to 500 mA through the interface. In the AC adapter configuration, an external resistor sets the maximum value of charge current.

The battery is charged in three phases: conditioning, constant current, and constant voltage. Charge is normally terminated based on minimum current. An internal charge timer provides a safety backup for charge termination. The TPS65014 automatically restarts the charge if the battery voltage falls below an internal threshold. The charger automatically enters sleep mode when both supplies are removed.

The serial interface can be used for dynamic voltage scaling, for collecting information on and controlling the battery charger status, for optionally controlling 2-LED driver outputs, a vibrator driver, masking interrupts, or for disabling, enabling, and setting the LDO output voltages. The interface is compatible with the fast- and standard-mode I2C specification, thus allowing transfers up to 400 kHz.

7.2 Functional Block Diagram

TPS65014 fbd_lvs551.gif

7.3 Feature Description

7.3.1 Step-Down Converters, VMAIN and VCORE

The TPS65014 incorporates two synchronous step-down converters operating typically at 1.25-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter power-save mode and operate with pulse frequency modulation (PFM). The main converter is capable of delivering 1-A output current and the core converter is capable of delivering 400 mA.

The converter output voltages are programmed through the VDCDC1 and VDCDC2 registers in the serial interface. The main converter defaults to 3-V or 3.3-V output voltage depending on the DEFMAIN configuration pin, if DEFMAIN is tied to ground, the default is 3 V; if it is tied to VCC, the default is 3.3 V. The core converter defaults to either 1.5 V or 1.8 V, depending on whether the DEFCORE configuration pin is tied to GND or to VCC, respectively. Both the main and core output voltages can subsequently be reprogrammed after start-up through the serial interface. In addition, the LOW_PWR pin can be used either to lower the core voltage to a value defined in the VDCDC2 register when the application processor is in deep sleep mode, or to disable the core converter. An active signal at LOW_PWR is ignored if the ENABLE_LP bit is not set in the VDCDC1 register.

The step-down converter outputs (when enabled) are monitored by power-good comparators, the outputs of which are available through the serial interface. The outputs of the DC-DC converters can be optionally discharged when the DC-DC converters are disabled.

During PWM operation, the converters use a fast response voltage-mode controller scheme with input voltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle, initiated by the clock signal, the P-channel MOSFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the dead time preventing current shoot through, the N-channel MOSFET rectifier is turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel switch.

The error amplifier, together with the input voltage, determines the rise time of the saw-tooth generator, and therefore any change in input voltage or output voltage directly controls the duty cycle of the converter, giving a good line and load transient regulation.

The two DC-DC converters operate synchronized to each other, with the MAIN converter as the master. A 270° phase shift between the MAIN switch turnon and the CORE switch turnon decreases the input RMS current, and smaller input capacitors can be used. This is optimized for a typical application where the MAIN converter regulates a Li-ion battery voltage of 3.7 V to 3.3 V and the CORE from 3.7 V to 1.5 V.

7.3.1.1 Forced PWM

The core and main converters are forced into PWM mode by setting bit 7 in the VDCDC1 register. This feature is used to minimize ripple on the output voltages.

7.3.1.2 Dynamic Voltage Positioning

As described in the power-save mode operation sections and as detailed in Figure 11, the output voltage is typically 1.2% above the nominal output voltage at light load currents, as the device is in power-save mode. This gives additional headroom for the voltage drop during a load transient from light load to full load. During a load transient from full load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel rectifier switch.

7.3.1.3 Soft-Start

Both converters have an internal soft-start circuit that limits the inrush current during start-up. The soft start is implemented as a digital circuit, increasing the switch current in 4 steps up to the typical maximum switch current limit of 700 mA (core) and 1.75 A (main). Therefore, the start-up time mainly depends on the output capacitor and load current.

7.3.1.4 100% Duty Cycle Low Dropout Operation

The TPS65014 converters offer a low input to output voltage difference while maintaining operation with the use of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage and is calculated in Equation 1:

Equation 1. TPS65014 Q_VI_min_lvs551.gif

where

  • IO(max) = maximum output current plus inductor ripple current
  • rDS(on)max = maximum P-channel switch rDSon
  • RL = DC resistance of the inductor
  • VO(max) = nominal output voltage plus maximum output voltage tolerance

7.3.1.5 Active Discharge When Disabled

When the CORE and MAIN converters are disabled, due to an UVLO, BATT_COVER, or OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is individually enabled through the VDCDC1 and VDCDC2 registers in the serial interface. When this feature is enabled, the core and main outputs are discharged by a 400-Ω (typical) load.

7.3.1.6 Power-Good Monitoring

Both the MAIN and CORE converters have power-good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these comparators are available in the REGSTATUS register through the serial interface. A maskable interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when the converters are disabled. The status of the power-good comparator for VMAIN is used to generate the RESPWRON signal.

7.3.1.7 Overtemperature Shutdown

The MAIN and CORE converters are automatically shut down if the temperature exceeds the trip point (see Electrical Characteristics). This detection is only active if the converters are in PWM mode, either by setting FPWM = 1, or if the output current is high enough that the device runs in PWM mode automatically.

7.3.2 Low-Dropout Voltage Regulators

The low-dropout voltage regulators are designed to operate with low value ceramic input and output capacitors. They operate with input voltages down to 1.8 V. The LDOs offer a maximum dropout voltage of 300 mV at rated output current. Each LDO has a current limit feature. Both LDOs are enabled per default; both LDOs can be disabled or programmed through the serial interface using the VREGS1 register. The LDO outputs (when enabled) are monitored by power-good comparators, the outputs of which are available through the serial interface. The LDOs also have reverse conduction prevention when disabled. This allows the possibility to connect external regulators in parallel in systems with a backup battery.

7.3.2.1 Power-Good Monitoring

Both the LDO1 and LDO2 linear regulators have power-good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these comparators are available in the REGSTATUS register through the serial interface. An interrupt is generated when any voltage rail drops below the 10% threshold. The LDO2 comparator is disabled when LDO2 is disabled.

7.3.2.2 Enabling and Sequencing

Enabling and sequencing of the DC-DC converters and LDOs are described in the power-up sequencing section. The OMAP1510 processor from Texas Instruments requires that the core power supply is enabled before the I/O power supply, which means that the CORE converter should power up before the MAIN converter. This is achieved by connecting PS_SEQ to GND.

7.3.3 Undervoltage Lockout

The undervoltage lockout circuit for the four regulators on TPS65014 prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. Basically, it prevents the converter from turning on the power switch or rectifier FET under undefined conditions. The undervoltage threshold voltage is set by default to 2.75 V. After power up, the threshold voltage can be reprogrammed through the serial interface. The undervoltage lockout comparator compares the voltage on the VCC pin with the UVLO threshold. When the VCC voltage drops below this threshold, the TPS65014 sets the PWRFAIL pin low and after a time t(UVLO) disables the voltage regulators in the sequence defined by PS_SEQ. The same procedure is followed when the TPS65014 detects that its junction temperature has exceeded the overtemperature threshold, typically 160°C, with a delay t(overtemp). The TPS65014 automatically restarts when the UVLO (or overtemperature) condition is no longer present.

The battery charger circuit has a separate UVLO circuit with a threshold of typically 2.5 V, which is compared with the voltage on AC and USB supply pins.

7.3.4 Power-Up Sequencing

The TPS65014 power-up sequencing is designed to allow the maximum flexibility without generating excessive logistical or system complexity. The relevant control pins are described in Table 2.

Table 2. Control Pins

PIN NAME INPUT/OUTPUT FUNCTION
PS_SEQ I Input signal indicating power-up and power-down sequence of the switching converters. PS_SEQ = 0 forces the core regulator to ramp up first and down last. PS_SEQ = 1 forces the main regulator to ramp up first and down last.
DEFCORE I Defines the default voltage of the VCORE switching converter. DEFCORE = 0 defaults VCORE to 1.5 V, DEFCORE = VCC defaults VCORE to 1.8 V.
DEFMAIN I Defines the default voltage of the VMAIN switching converter. DEFMAIN = 0 defaults VMAIN to 3 V, DEFMAIN = VCC defaults VMAIN to 3.3 V.
LOW_PWR I The LOW_PWR pin is used to lower VCORE to the preset voltage in the VDCDC2 register when the processor is in deep sleep mode. Alternatively, VCORE can be disabled in low power mode if the LP_COREOFF bit is set in the VDCDC2 register. LOW_PWR is ignored if the ENABLE LP bit is not set in the VDCDC1 register. The TPS65014 uses the rising edge of the internal signal formed by a logical AND of LOW_PWR and ENABLE LP to enter low power mode. TPS65014 is forced out of low power mode by deasserting LOW_PWR, by resetting ENABLE LP to 0, by activating the PB_ONOFF pin or by activating the HOT_RESET pin. There are two ways to get the device back into low power mode: a) toggle the LOW_PWR pin, or b) toggle the low power bit when the LOW_PWR pin is held high. The LOW_PWR pin is also used to set the TPS65014 into WAIT mode. If USB or AC is present, the AUA bit (CHCONFIG<7>) must be set to enter the WAIT mode, see Figure 23.
PB_ONOFF I PB_ONOFF can be used to exit the low power mode and return the core voltage to the value before low power mode was entered. If PB_ONOFF is used to exit the low power mode, then the low power mode can be reentered by toggling the LOW_PWR pin or by toggling the low power bit when the LOW_PWR pin is held high. A 1-MΩ pulldown resistor is integrated in TPS65014. PB_ONOFF is internally de-bounced by the TPS65014. A maskable interrupt is generated when PB_ONOFF is activated.
HOT_RESET I The HOT_RESET pin has a similar functionality to the PB_ONOFF pin. In addition, it generates a reset (MPU_RESET) for the MPU when the VCORE voltage is in regulation. HOT_RESET does not alter any TPS65014 settings unless low power mode was active in which case it is exited. A 1-MΩ pullup resistor to VCC is integrated in TPS65014. HOT_RESET is internally de-bounced by the TPS65014.
BATT_COVER I The BATT_COVER pin is used as an early warning that the main battery is about to be removed. BATT_COVER = VCC indicates that the cover is in place, BATT_COVER = 0 indicates that the cover is not in place. TPS65014 generates a maskable interrupt when the BATT_COVER pin goes low. PWRFAIL is also held low when BATT_COVER goes low. This feature may be disabled by tying BATT_COVER permanently to VCC. The TPS65014 shuts down the main and the core converter and sets the LDOs into low power mode. A 2-MΩ pulldown resistor is integrated in the TPS65014 at the BATT_COVER pin. BATT_COVER is internally de-bounced by the TPS65014.
RESPWRON O RESPWRON is held low while the switching converters (and any LDOs defined as default on) are starting up. It is determined by the state of MAIN's output voltage; when the voltage is higher than the power-good comparator threshold; then RESPWRON is high when VMAIN is low; then RESPWRON is low. RESPWRON is held low for tn(RESPWRON) seconds after VMAIN has settled.
MPU_RESET O MPU_RESET can be used to reset the processor if the user activates the HOT_RESET button. The MPU_RESET output is active for t(MPU_nRESET) sec. It also forces TPS65014 to leave low power mode. MPU_RESET is also held low as long as RESPWRON is held low.
PWRFAIL O PWRFAIL indicates when VCC < V(UVLO), when the TPS65014 is about to shut down due to an internal overtemperature condition or when BATT_COVER is low. PWRFAIL is also held low as long as RESPWRON is held low.
TPOR I TPOR is used to set the delay time for the RESPWRON reset signal.
TPOR = 0 sets the delay time to 100 ms. TPOR = 1 sets the delay time to 1 s.

Figure 23 shows the state diagram for TPS65014 power sequencing. The charger function is not shown in the state diagram because this function is independent of these states.

TPS65014 ai_diagram_lvs551.gif Figure 23. TPS65014 Power-On State Diagram

7.3.4.1 TPS65014 Power State Descriptions

7.3.4.1.1 State 1: No Power

No batteries are connected to the TPS65014. When main power is applied, the bandgap reference, LDOs, and UVLO comparator start up. The RESPWRON, PWRFAIL, INT, and MPU_RESET signals are held low. When BATT_COVER goes high (de-bounced internally by the TPS65014), indicating that the battery cover has been put in place and if VCC > UVLO, the power supplies are ramped in the sequence defined by PS_SEQ. RESPWRON, PWRFAIL, INT, and MPU_RESET are released when the RESPWRON timer has timed out after tn(RESPWRON) seconds. If VCC remains valid and no OVERTEMP condition occurs, then the TPS65014 arrives in State 2: ON. If VCC < UVLO, the TPS65014 keeps the bandgap reference and UVLO comparator active such that when VCC>UVLO (during battery charge), the supplies are automatically activated.

7.3.4.1.2 State 2: ON

In this state, the TPS65014 is fired up and ready for operation. The switching converter output voltages can be programmed. The LDOs can be disabled or programmed. The TPS65014 can exit this state due to an overtemperature condition, an undervoltage condition at VCC, BATT_COVER going low, or by the processor programming low power mode. State 2 is left temporarily if the user activates the HOT_RESET pin.

7.3.4.1.3 State 3: Low-Power Mode

This state is entered through the processor setting the ENABLE_LP bit in the serial interface and then raising the LOW_PWR pin. The TPS65014 uses the rising edge of the internal signal formed by a logical AND of the LOW_PWR and ENABLE LP signals to enter low power mode. The VMAIN switching converter remains active, but the VCORE converter may be disabled in low power mode through the serial interface by setting the LP_COREOFF bit in the VDCDC2 register. If left enabled, the VCORE voltage is set to the value predefined by the CORELP0/1 bits in the VDCDC2 register. The LDO1OFF/nSLP and LDO2OFF/nSLP bits in the VREGS1 register determine whether the LDOs are turned off or put in a reduced power mode (transient speed-up circuitry disabled in order to minimize quiescent current) in low power mode. All TPS65014 features remain addressable through the serial interface. The TPS65014 can exit this state either due to an undervoltage condition at VCC, due to BATT_COVER going low, due to an OVERTEMP condition, by the processor deasserting the LOW_POWER pin, or by the user activating the HOT_RESET pin or the PB_ONOFF pin.

7.3.4.1.4 State 4: Shutdown

There are two scenarios for entering this state. The first is from State 1: No Power. As soon as main battery power is applied, the device automatically enters the WAIT mode.

The second scenario occurs when the device is in ON mode and the processor initiates a shutdown by resetting the ENABLE SUPPLY bit in the VDCDC1 register (ENABLE_LP must be high), and then raising the LOW_PWR pin. When this happens, the power rails are ramped down in the predefined sequence, and all circuitry is then disabled. In this state, the TPS65014 waits for the PB_ONOFF or HOT_RESET pin to be activated before enabling any of the supply rails. When the PB_ONOFF or HOT_RESET pin is activated, the TPS65014 powers up the supplies according to the same constraints as at the initial application of power. Complete shutdown is only achieved by setting the LDO1OFF/nSLP and LDO2OFF/nSLP bits high in the VREGS1 register before activating the shutdown.

In this case, the I2C interface is deactivated, and the registers are reset to their default value after leaving the WAIT mode.

To enter the WAIT mode when USB or AC is present, set the AUA bit (CHCONFIG<7>). The WAIT mode is automatically left if bit 7 in register CHCONFIG is set to 0 (default), and a voltage is present at either the AC pin or the USB pin in the appropriate range for charging, and the voltage at VCC is above the UVLO threshold. This feature allows the converters to start up automatically if the device is plugged in for charging.

If all supplies are turned off in WAIT mode, the internal bandgap is switched off, and the internal registers are reset to their default state when the device returns to ON mode.

Table 3 lists possible configurations in LOW POWER mode and WAIT mode.

Table 3. TPS65014 Possible Configurations(1)

CONVERTER MAIN CORE LDO1 LDO2
LOW POWER mode 1 0/1 0/1 0/1
WAIT mode 0 0 0/1 0/1
(1) 0 = converter is disabled
1 = converter is enabled

Table 4 indicates the typical quiescent-current consumption in each power state.

Table 4. TPS65014 Typical Current Consumption

STATE TOTAL QUIESCENT
CURRENT
QUIESCENT CURRENT BREAKDOWN
1 0
2 30 µA–70 µA VMAIN (12 µA) + VCORE (12 µA) + LDOs (20 µA each, max 2) + UVLO + reference + PowerGood
3 30 µA–55 µA VMAIN (12 µA) + VCORE (12 µA) + LDOs (10 µA each, max 2) + UVLO + reference + PowerGood
4 13 µA UVLO + reference circuitry
TPS65014 ai_state12_lvs551.gif

NOTE:

Valid for LDO1 supplied from VMAIN as described earlier in this Application Section.
Figure 24. State 1 to State 2 Transition (PS_SEQ = 0, VCC > VUVLO + HYST)

If 2.4 ms after application VCC is still below the default UVLO threshold (3.15 V for VCC rising), then start up is as shown in Figure 25.

TPS65014 ai_state142_lvs551.gif

NOTE:

Valid for LDO1 supplied from VMAIN as described earlier in this Application Section
Figure 25. State 1 to State 4 to State 2 Transition (Power-Up Behavior When Charge Voltage is Applied)
TPS65014 ai_state242_lvs551.gif

NOTE:

Valid for LDO1 supplied from VMAIN as described earlier in this Application Section
Figure 26. State 2 to State 4 Transition
TPS65014 ai_state23_lvs551.gif

NOTE:

VCORE Lowered, LDO2 Disabled

NOTE:

Subsequent State 3 to State 2 Transition When LOW POWER Is Deasserted.
Figure 27. State 2 to State 3 Transition
TPS65014 ai_state32PB_lvs551.gif

NOTE:

PB_ONFF Activated (See Interrupt Management for INT Behavior)
Figure 28. State 3 to State 2 Transition
TPS65014 ai_state32HT_lvs551.gif

NOTE:

HOT_RESET Activated (See Interrupt Management for INT Behavior)
Figure 29. State 3 to State 2 Transition
TPS65014 ai_state1-4_lvs551.gif Figure 30. State 1 to State 4 Transition

7.3.5 System Reset and Control Signals

The RESPWRON signal is used as a global reset for the application. It is an open-drain output. The RESPWRON signal is generated according to the power good comparator linked to VMAIN and remains low for tn(RESPWRON) seconds after VMAIN has stabilized. When RESPWRON is low, PWRFAIL, MPU_RESET, and INT are also held low.

If the output voltage of MAIN is less than 90% of its nominal value, as RESPWRON is generated, and if the output voltage of MAIN is programmed to a higher value, which causes the output voltage to fall out of the 90% window, then a RESPWRON signal is generated.

The PWRFAIL signal indicates when VCC < UVLO or when the TPS65014 junction temperature has exceeded a reliable value or if BATT_COVER is taken low. This open-drain output can be connected at a fast interrupt pin for immediate attention by the application processor. All supplies are disabled t(uvlo), t(overtemp), or t(batt_cover) seconds after PWRFAIL has gone low, giving time for the application processor to shut down cleanly.

BATT_COVER is used to detect whether the battery cover is in place or not. If the battery cover is removed, the TPS65014 generates a warning to the processor that the battery is likely to be removed and that it may be prudent to shut down the system. If not required, this feature may be disabled by connecting the BATT_COVER pin to the VCC pin. BATT_COVER is de-bounced internally. Typical de-bounce time is 56 ms. BATT_COVER has an internal 2-MΩ pulldown resistor.

The HOT_RESET input is used to generate an MPU_RESET signal for the application processor. The HOT_RESET pin could be connected to a user-activated button in the application. It can also be used to exit low power mode. In this case, the TPS65014 waits until the VCORE voltage has stabilized before generating the MPU_RESET pulse. The MPU_RESET pulse is active low for t(mpu_nreset) seconds. HOT_RESET has an internal 1-MΩ pullup resistor to VCC.

The PB_ONOFF input can be used to exit LOW POWER MODE. It is typically driven by a user-activated pushbutton in the application. Both HOT_RESET and PB_ONOFF are de-bounced internally by the TPS65014. Typical debounce time is 56 ms. PB_ONOFF has an internal 1-MΩ pulldown resistor.

PB_ONOFF, BATT_COVER and UVLO events also cause a normal, maskable interrupt to be generated and are noted in the REGSTATUS register.

7.3.6 Vibrator Driver

The VIB open-drain output is provided to drive a vibrator motor, controlled through the serial interface register VDCDC2. It has a maximum dropout of 0.5 V at 100-mA load. Typically, an external resistor is required to limit the motor current and a freewheel diode to limit the VIB overshoot voltage at turnoff.

7.3.7 LED2 Output

The LED2 output can be programmed in the same way as the PG output to blink or to be permanently on or off. The LED2_ON and LED2_PER registers are used to control the blink rate. For both PG and LED2, the minimum blink-on time is 10 ms, and this can be increased in 127 10-ms steps to 1280 ms. For both PG and LED2, the minimum blink period is 100 ms, and this can be increased in 127 100-ms steps to 12800 ms.

7.3.8 Interrupt Management

The open-drain INT pin is used to combine and report all possible conditions through a single pin. Battery and chip temperature faults, precharge timeout, charge timeout, taper timeout, and termination current are each capable of setting INT low, that is, active. INT can also be activated if any of the regulators are below the regulation threshold. Interrupts can also be generated by any of the GPIO pins programmed to be inputs. These inputs can be programmed to generate an interrupt either at the rising or falling edge of the input signal. It is possible to mask an interrupt from any of these conditions individually by setting the appropriate bits in the MASK1, MASK2, or MASK3 registers. By default, all interrupts are masked. Interrupts are stored in the CHGSTATUS, REGSTATUS, and DEFGPIO registers in the serial interface. CHGSTATUS and REGSTATUS interrupts are acknowledged by reading these registers. If a 1 is present in any location, then the TPS65014 automatically sets the corresponding bit in the ACKINT1 or ACKINT2 registers and releases the INT pin. The ACKINT register contents are self-clearing when the condition, which caused the interrupt, is removed. The applications processor should not normally need to access the ACKINT1 or ACKINT2 registers.

Interrupt events are always captured; thus when an interrupt source is unmasked, INT may immediately go active due to a previous interrupt condition. This can be prevented by first reading the relevant STATUS register before unmasking the interrupt source.

If an interrupt condition occurs, then the INT pin is set low. The CHGSTATUS, REGSTATUS, and DEFGPIO registers should be read. Bit positions containing a 1 (or possibly a 0 in DEFGPIO) are noted by the CPU and the corresponding situation resolved. The reading of the CHGSTATUS and REGSTATUS registers automatically acknowledges any interrupt condition in those registers and blocks the path to the INT pin from the relevant bits. No interrupt should be missed during the read process because this process starts by latching the contents of the register before shifting them out at SDAT. Once the contents have been latched (which takes a couple of nanoseconds), the register is free to capture new interrupt conditions. Thus, for practical purposes the probability of missing anything is zero.

The following describes how registers 0x01 (CHGSTATUS) and 0x02 (REGSTATUS) are handled:

  • CHGSTATUS(5,0) are positive edge set. Read of set CHGSTATUS(5,0) bits sets ACKINT1(5,0) bits.
  • CHGSTATUS(7-6,4-1) are level set. Read of set CHGSTATUS(7-6,4-1) bits sets ACKINT1(7-6,4-1) bits.
  • CHGSTATUS(5,0) clear when input signal low, and ACKINT1(5,0) bits are already set.
  • CHGSTATUS(7-6,4-1) clear when input signal is low.
  • ACKINT1(7-0) clear when CHGSTATUS(7-0) is clear.
  • REGSTATUS(7-5) are positive edge set. Read of set REGSTATUS(7-5) bits sets ACKINT2(7-5) bits.
  • REGSTATUS(3-0) are level set. Read of set REGSTATUS(3-0) bits sets ACKINT2(3-0) bits.
  • REGSTATUS(7-5) clear when input signal low, and ACKINT1(7-5) bit are already set.
  • REGSTATUS(3-0) clear when input signal is low.
  • ACKINT2(7-0) clear when REGSTATUS(7-0) is clear.

The following describes the function of the 0x05 (ACKINT1) and 0x06 (ACKINT2) registers. These are not usually written to by the CPU because the TPS65014 internally sets/clears these registers:

  • ACKINT1(7:0): Bit is set when the corresponding CHGSTATUS set bit is read through I2C.
  • ACKINT1(7:0): Bit is cleared when the corresponding CHGSTATUS set bit clears.
  • ACKINT2(7:0): Bit is set when the corresponding REGSTATUS set bit is read through I2C.
  • ACKINT2(7:0): Bit is cleared when the corresponding REGSTATUS set bit clears.
  • ACKINT1(7:0): A bit set masks the corresponding CHGSTATUS bit from INT.
  • ACKINT2(7:0): A bit set masks the corresponding REGSTATUS bit from INT.

The following describes the function of the 0x03 (MASK1), 0x04 (MASK2) and 0x0F (MASK3) registers:

  • MASK1(7:0): A bit set in this register masks CHGSTATUS from INT.
  • MASK2(7:0): A bit set in this register masks REGSTATUS from INT.
  • MASK3(7:4): A bit set in this register detects a rising edge on GPIO.
  • MASK3(7:4): A bit cleared in this register detects a falling edge on GPIO.
  • MASK3(3:0): A bit set in this register clears GPIO Detect signal from INT.

GPIO interrupts are located by reading the 0x10 (DEFGPIO) register. The application CPU stores, or can read from DEFGPIO<7:4>, which GPIO is set to input or output. This information together with the information on which edge the interrupt was generated (the CPU either knows this or can read it from MASK3<7:4>) determines whether the CPU is looking for a 0 or a 1 in DEFGPIO<3:0>. A GPIO interrupt is blocked from the INT pin by setting the relevant MASK3<3:0> bit; this must be done by the CPU, there is no auto-acknowledge for the GPIO interrupts.

7.3.9 Serial Interface

The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above 2 V. The TPS65014 has a 7-bit address with the LSB set by the IFLSB pin; this allows the connection of two devices with the same address to the same bus. The 6 MSBs are 100100. Attempting to read data from register addresses not listed in this section results in FFh being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65014 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65014 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65014 device must leave the data line high to enable the master to generate the stop condition.

The I2C interface accepts data as soon as the voltage at VCC is higher than the undervoltage lockout threshold and one power rail of the converter (main, core, or one of the LDOs) is operating. Therefore, the I2C interface is not operating after applying the battery voltage as the device automatically enters the WAIT mode with all rails off.

When the device is in WAIT mode, the I2C registers are reset to their default values if all voltage rails are off. If the device is in WAIT mode and one power rail is left on, the I2C interface is operating and the registers are not reset after leaving the WAIT mode.

TPS65014 ai_bit_lvs551.gif Figure 31. Bit Transfer on the Serial Interface
TPS65014 ai_st_stop_lvs551.gif Figure 32. START and STOP Conditions
TPS65014 ai_write_dev_lvs551.gif

NOTE:

SLAVE = TPS65014
Figure 33. Serial Interface WRITE to TPS65014 Device
TPS65014 ai_read_proA_lvs551.gif

NOTE:

SLAVE = TPS65014
Figure 34. Serial Interface READ From TPS65014: Protocol A
TPS65014 ai_read_proB_lvs551.gif

NOTE:

SLAVE = TPS65014
Figure 35. Serial Interface READ From TPS65014: Protocol B
TPS65014 ai_time_diag_lvs551.gif Figure 36. Serial Interface Timing Diagram

7.4 Device Functional Modes

7.4.1 Power Save Mode Operation

As the load current decreases, the converter enters the power-save mode operation. During power-save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency.

To optimize the converter efficiency at light load, the average current is monitored; if in PWM mode, the inductor current remains below a certain threshold, and then power-save mode is entered. The typical threshold can be calculated as in Equation 2:

Equation 2. TPS65014 Q_Iskip_lvs551.gif

During the power-save mode, the output voltage is monitored with the comparator by the thresholds comp low and comp high. As the output voltage falls below the comp low threshold, set to typically 0.8% above the nominal Vout, the P-channel switch turns on. The converter then runs at 50% of the nominal switching frequency. If the load is below the delivered current, then the output voltage rises until the comp high threshold is reached, typically 1.6% above the nominal Vout. At this point, all switching activity ceases, thus reducing the quiescent current to a minimum until the output voltage has dropped below comp low again. If the load current is greater than the delivered current, then the output voltage falls until it crosses the nominal output voltage threshold (comp low 2 threshold), whereupon power-save mode is exited, and the converter returns to PWM mode.

These control methods reduce the quiescent current typically to 12 µA per converter and the switching frequency to a minimum, achieving the highest converter efficiency. Setting the comparator thresholds to typically 0.8% and 1.6% above the nominal output voltage at light load current results in a dynamic voltage positioning achieving lower absolute voltage drops during heavy load transient changes. This allows the converters to operate with a small output capacitor of just 10 µF for the core and 22 µF for the main output and still have a low absolute voltage drop during heavy load transient changes. See Figure 37 for detailed operation of the power-save mode. The power-save mode can be disabled through the I2C interface to force the converters to stay in fixed frequency PWM mode.

TPS65014 ai_PSM_thre_lvs551.gif Figure 37. Power-Save Mode Thresholds and Dynamic Voltage Positioning

7.4.2 Sleep Mode

The TPS65014 charger enters the low-power sleep mode if both input sources are removed from the circuit. This feature prevents draining the battery during the absence of input power.

7.5 Register Maps

7.5.1 CHGSTATUS Register (offset = 01h) (reset: 00h)

Bits 1-4 may be reset through the serial interface in order to force a reset of the charger. Any attempt to write to Bit 0 and Bits 5-7 is ignored. A 1 in <7:0> sets the INT pin active unless the corresponding bit in the MASK register is set.

Figure 38. CHGSTATUS Register
7 6 5 4 3 2 1 0
USB Charge AC Charge Thermal
Suspend
Term Current Taper Timeout Chg Timeout Prechg Timeout BattTemp
Error
R-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5. CHGSTATUS Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 USB charge R 0h

0h = Inactive

1h = USB source is present and in the range valid for charging. B7 remains active as long as the charge source is present.

6 AC charge R 0h

0h = Wall plug source is not present and/or not in the range valid for charging

1h = Wall plug source is present and in the range valid for charging. B6 remains active as long as the charge source is present.

5 Thermal suspend R 0h

0h = Charging is allowed

1h = Charging is momentarily suspended due to excessive power dissipation on chip.

4 Term current R 0h

0h = Charging, charge termination current threshold has not been crossed.

1h = Charge termination current threshold has been crossed and charging has been stopped. This can be due to a battery reaching full capacity, or to a battery removal condition.

3 Taper Timeout R/W 0h

If CHCONFIG<5>=0: Bit 3 equals the output of the taper voltage comparator directly, without any timer delay.

If CHCONFIG<5>=1: there is a delay of 30 minutes because the timers have to time out first.

0h = Charging, timers did not time out

1h = One of the timers has timed out and charging has been terminated.

2 Chg Timeout R/W 0h

If CHCONFIG<5>=0: Bit 3 equals the output of the taper voltage comparator directly, without any timer delay.

If CHCONFIG<5>=1: there is a delay of 30 minutes because the timers have to time out first.

0h = Charging, timers did not time out

1h = One of the timers has timed out and charging has been terminated.



1 Prechg Timeout R/W 0h

If CHCONFIG<5>=0: Bit 3 equals the output of the taper voltage comparator directly, without any timer delay.

If CHCONFIG<5>=1: there is a delay of 30 minutes because the timers have to time out first.

0h = Charging, timers did not time out

1h = One of the timers has timed out and charging has been terminated.

0 BattTempError R 0h

Battery temperature error

  • 0 = Battery temperature is inside the allowed range and that charging is allowed.
  • 1 = Battery temperature is outside of the allowed range and that charging is suspended.

7.5.2 REGSTATUS Register (offset = 02h) (reset: 00h)

A rising edge in the REGSTATUS register contents causes INT to be driven low if it is not masked in the MASK2.

Figure 39. REGSTATUS Register
7 6 5 4 3 2 1 0
PB_ONOFF BATT_COVER UVLO Rsvd PGOOD LDO2 PGOOD LDO1 PGOOD MAIN PGOOD CORE
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. REGSTATUS Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 PB_ONOFF R 0h

0h = Inactive

1h = User activated the PB_ONOFF switch to request that all rails are shut down.

6 BATT_COVER R 0h

0h = BATT_COVER pin is high

1h = BATT_COVER pin is low

5 UVLO R 0h

0h = Voltage at the VCC pin above UVLO threshold

1h = Voltage at the VCC pin has dropped below the UVLO threshold

4 Reserved R 0h
3 PGOOD LDO2 R 0h

0h = LDO2 output in regulation, or LDO2 disabled with VREGS1 <7> = 0

1h = LDO2 output out of regulation

2 PGOOD LDO1 R 0h

0h = LDO1 output in regulation, or LDO1 disabled with VREGS1 <3> = 0

1h = LDO1 output out of regulation

1 PGOOD MAIN R 0h

0h = Main converter output in regulation

1h = Main converter output out of regulation

0 PGOOD CORE R 0h

0h = Core converter output in regulation

1h = Core converter output out of regulation, or VDCDC2 <7> = 1 in low power mode

7.5.3 MASK1 Register (offset = 03h) (reset: FFh)

The MASK1 register is used to mask all or any of the conditions in the corresponding CHGSTATUS<7:0> positions indicated at the INT pin. Default is to mask all.

Figure 40. MASK1 Register
7 6 5 4 3 2 1 0
Mask USB Mask AC Mask Thermal
Suspend
Mask Term Mask Taper Mask Chg Mask Prechg Mask BattTemp
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. MASK1 Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Mask USB R/W 1h INT Mask for Bit 7 in CHGSTATUS register. Refer to Table 5.
6 Mask AC R/W 1h INT Mask for Bit 6 in CHGSTATUS register. Refer to Table 5.
5 Mask Thermal Suspend R/W 1h INT Mask for Bit 5 in CHGSTATUS register. Refer to Table 5.
4 Mask Term R/W 1h INT Mask for Bit 4 in CHGSTATUS register. Refer to Table 5.
3 Mask Taper R/W 1h INT Mask for Bit 3 in CHGSTATUS register. Refer to Table 5.
2 Mask Chg R/W 1h INT Mask for Bit 2 in CHGSTATUS register. Refer to Table 5.
1 Mask Prechg R/W 1h INT Mask for Bit 1 in CHGSTATUS register. Refer to Table 5.
0 Mask BattTemp R/W 1h INT Mask for Bit 0 in CHGSTATUS register. Refer to Table 5.

7.5.4 MASK2 Register (offset = 04h) (reset: FFh)

The MASK2 register is used to mask all or any of the conditions in the corresponding REGSTATUS<7:0> positions indicated at the INT pin. Default is to mask all.

Figure 41. MASK2 Register
7 6 5 4 3 2 1 0
Mask PB_ONOFF Mask BATT_COVER Mask UVLO Rsvd Mask PGOOD LDO2 Mask PGOOD LDO1 Mask PGOOD MAIN Mask PGOOD CORE
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. MASK2 Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Mask PB_ONOFF R/W 1h INT Mask for Bit 7 in REGSTATUS register. Refer to Table 6.
6 Mask BATT_COVER R/W 1h INT Mask for Bit 6 in REGSTATUS register. Refer to Table 6.
5 Mask UVLO R/W 1h INT Mask for Bit 5 in REGSTATUS register. Refer to Table 6.
4 Reserved R/W 1h Reserved
3 Mask PGOOD LDO2 R/W 1h INT Mask for Bit 3 in REGSTATUS register. Refer to Table 6.
2 Mask PGOOD LDO1 R/W 1h INT Mask for Bit 2 in REGSTATUS register. Refer to Table 6.
1 Mask PGOOD MAIN R/W 1h INT Mask for Bit 1 in REGSTATUS register. Refer to Table 6.
0 Mask PGOOD CORE R/W 1h INT Mask for Bit 0 in REGSTATUS register. Refer to Table 6.

7.5.5 ACKINT1 Register (offset = 05h) (reset: 00h)

The ACKINT1 register is internally used to acknowledge any of the interrupts in the corresponding CHGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes high, else it will remain low. A 1 at any position in ACKINT1 is automatically cleared when the corresponding interrupt condition in CHGSTATUS is removed. The application processor should not normally need to access the ACKINT1 register.

Figure 42. ACKINT1 Register
7 6 5 4 3 2 1 0
Ack USB Ack AC Ack Thermal Shutdown Ack Term Ack Taper Ack Chg Ack Prechg Ack BattTemp
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. ACKINT1 Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Ack USB R 0h Internal ack for Bit 7 in CHGSTATUS register. Refer to Table 5.
6 Ack AC R 0h Internal ack for Bit 6 in CHGSTATUS register. Refer to Table 5.
5 Ack Thermal Shutdown R 0h Internal ack for Bit 5 in CHGSTATUS register. Refer to Table 5.
4 Ack Term R 0h Internal ack for Bit 4 in CHGSTATUS register. Refer to Table 5.
3 Ack Taper R 0h Internal ack for Bit 3 in CHGSTATUS register. Refer to Table 5.
2 Ack Chg R 0h Internal ack for Bit 2 in CHGSTATUS register. Refer to Table 5.
1 Ack Prechg R 0h Internal ack for Bit 1 in CHGSTATUS register. Refer to Table 5.
0 Ack BattTemp R 0h Internal ack for Bit 0 in CHGSTATUS register. Refer to Table 5.

7.5.6 ACKINT2 Register (offset: 06h) (reset: 00h)

The ACKINT2 register is internally used to acknowledge any of the interrupts in the corresponding REGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes high, else it will remain low. A 1 at any position in ACKINT2 is automatically cleared when the corresponding interrupt condition in REGSTATUS is removed. The application processor should not normally need to access the ACKINT2 register.

Figure 43. ACKINT2 Register
7 6 5 4 3 2 1 0
Ack PB_ONOFF Ack BATT_
COVER
Ack UVLO Rsvd Ack PGOOD LDO2 Ack PGOOD LDO1 Ack PGOOD MAIN Ack PGOOD CORE
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. ACKINT2 Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 Ack PB_ONOFF R 0h Internal ack for Bit 7 in REGSTATUS register. Refer to Table 6.
6 Ack BATT_
COVER
R 0h Internal ack for Bit 6 in REGSTATUS register. Refer to Table 6.
5 Ack UVLO R 0h Internal ack for Bit 5 in REGSTATUS register. Refer to Table 6.
4 Reserved R 0h Reserved
3 Ack PGOOD LDO2 R 0h Internal ack for Bit 3 in REGSTATUS register. Refer to Table 6.
2 Ack PGOOD LDO1 R 0h Internal ack for Bit 2 in REGSTATUS register. Refer to Table 6.
1 Ack PGOOD MAIN R 0h Internal ack for Bit 1 in REGSTATUS register. Refer to Table 6.
0 Ack PGOOD CORE R 0h Internal ack for Bit 0 in REGSTATUS register. Refer to Table 6.

7.5.7 CHGCONFIG Register (offset: 07h) (reset: 1Bh)

The CHGCONFIG register is used to configure the charger.

Figure 44. CHGCONFIG Register
7 6 5 4 3 2 1 0
AUA Charger reset Fast charge timer + taper timer enabled MSB charge current LSB charge current USB / 100 mA 500 mA USB charge allowed Charge
enable
R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. CHGCONFIG Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 AUA R/W 0h

0h = If a voltage is present at AC or USB in the appropriate range for charging, and if VCC > UVLO, the TPS65014 is forced into ON mode. The WAIT mode is disabled.

1h = If a voltage source at AC or USB is present, the WAIT mode is enabled, and the TPS65014 does not automatically turn on the converters.

6 Charger reset R/W 0h

Clears all the timers in the charger and forces a restart of the charge algorithm.

0/1 = This bit must be set and then reset through the serial interface.

5 Fast charge timer + taper timer enabled R/W 0h

0h = Fast charge timer disabled (default), CHSTATUS <3>= status of the taper detect comparator output.

1h = Enables the fast charge timer and taper timer. CHSTATUS <3>= status of the taper timer.

4 MSB charge current R/W 1h Used to set the constant current in the current regulation phase. See Table 12.
3 LSB charge current R/W 1h Used to set the constant current in the current regulation phase. See Table 12.
2 USB / 100 mA 500 mA R/W 0h

0h = Sets the USB charging current to max 100 mA.

1h = Sets the USB charging current to max 500 mA. B2 is ignored if B1 = 0.

1 USB charge allowed R/W 1h

0h = Prevents any charging from the USB input.

1h = Charging from the USB input is allowed.

0 Charge
enable
R/W 1h

0h = Charging is not allowed.

1h = Charger is free to charge from either of the two input sources. If both sources are present and valid, the TPS65014 charges from the AC pin source.

Table 12. Charge Current Rate

B4:B3 CHARGE CURRENT RATE
11 Maximum current set by the external resistor at the ISET pin
10 75% of maximum
01 50% of maximum
00 25% of maximum

7.5.8 LED1_ON Register (offset: 08h) (reset: 00h)

The LED1_ON and LED1_PER registers can be used to take control of the PG open-drain output normally controlled by the charger.

Figure 45. LED1_ON Register
7 6 5 4 3 2 1 0
PG1 LED1 ON6 LED1 ON5 LED1 ON4 LED1 ON3 LED1 ON2 LED1 ON1 LED1 ON0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. LED1_ON Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 PG1 R/W 0h Control of the PG pin is determined by PG1 and PG2 according to the table under LED1_PER register
6-0 LED1 ONx R/W 0h LED1_ON[6:0] are used to program the on-time of the open-drain output transistor at the PG pin. The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on-time.

7.5.9 LED1_PER Register (offset: 09h) (reset: 00h)

Figure 46. LED1_PER Register
7 6 5 4 3 2 1 0
PG2 LED1 PER6 LED1 PER5 LED1 PER4 LED1 PER3 LED1 PER2 LED1 PER1 LED1 PER0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. LED1_PER Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 PG2 R/W 0h Control of the PG pin is determined by PG1 and PG2 according to Table 15. Default shown in bold.
6-0 LED1 PERx R/W 0h LED1_PER<6:0> are used to program the time period of the open-drain output transistor at the PG pin. The minimum period is typically 100 ms and one LSB corresponds to a 100-ms, step change in the period.

Table 15. Control of the PG Pin

PG1 PG2 BEHAVIOR OF PG OPEN-DRAIN OUTPUT
0 0 Under charger control
0 1 Blink
1 0 Off
1 1 Always On

7.5.10 LED2_ON Register (offset: 0Ah) (reset: 00h)

The LED2_ON and LED2_PER registers are used to control the LED2 open-drain output.

Figure 47. LED2_ON Register
7 6 5 4 3 2 1 0
LED21 LED2 ON6 LED2 ON5 LED2 ON4 LED2 ON3 LED2 ON2 LED2 ON1 LED2 ON0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. LED2_ON Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 LED21 R/W 0h Control is determined by LED21 and LED22 according to Table 18.
6-0 LED2 ONx R/W 0h LED2_ON<6:0> are used to program the on-time of the open-drain output transistor at the LED2 pin. The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms, step change in the on-time.

7.5.11 LED2_PER (offset: 0Bh) (reset: 00h)

Figure 48. LED2_PER Register
7 6 5 4 3 2 1 0
LED22 LED2 PER6 LED2 PER5 LED2 PER4 LED2 PER3 LED2 PER2 LED2 PER1 LED2 PER0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. LED2_PER Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 LED22 R/W 0h Control is determined by LED21 and LED22 according to Table 18.
6-0 LED2 PERx R/W 0h LED2_ON<6:0> are used to program the on-time of the open-drain output transistor at the LED2 pin. The minimum on-time is typically 100 ms and one LSB corresponds to a 100-ms, step change in the on-time.

Table 18. LED Control

LED21 LED22 BEHAVIOR OF LED2 OPEN-DRAIN OUTPUT
0 0 Off
0 1 Blink
1 0 Off
1 1 Always On

7.5.12 VDCDC1 Register (offset: 0Ch) (reset: 32h/33h)

The VDCDC1 register is used to program the VMAIN switching converter.

Figure 49. VDCDC1 Register
7 6 5 4 3 2 1 0
FPWM UVLO1 UVLO0 ENABLE SUPPLY ENABLE LP MAIN DISCHARGE MAIN1 MAIN0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. VDCDC1 Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 FPWM R/W 0h

Forced PWM mode for DC-DC converters.

0h = MAIN and the CORE DC-DC converter are allowed to switch into PFM mode.

1h = MAIN and the CORE DC-DC converter operate with forced fixed-frequency PWM mode and are not allowed to switch into PFM mode, at light load.

6-5 UVLOx R/W 0h The undervoltage threshold voltage is set by UVLO1 and UVLO0 according to Table 20, with the default value in bold.
4 ENABLE SUPPLY R/W 1h

Selects between LOW POWER mode and WAIT mode

0h = WAIT mode allowed, activated when LOW_PWR pin = 1 and VDCDC1 <3>= 1.

1h = The TPS65014 enters LOW POWER mode when LOW_PWR pin = 1 and VDCDC1 <3>= 1

3 ENABLE LP R/W 0h

0h = Disables the low power function of the LOW_PWR pin

1h = Enables the low power function of the LOW_PWR pin.

2 MAIN DISCHARGE R/W 0h

0h = disables the active discharge of the VMAIN converter output.

1h = enables the active discharge of the VMAIN converter output, when the converter is disabled (that is, in WAIT mode).

1-0 MAINx R/W 1h The VMAIN converter output voltages are set according to Table 21, with the default values in bold set by the DEFMAIN pin. The default voltage can subsequently be overwritten through the serial interface after start-up.

Table 20. Undervoltage Threshold Voltage

UVLO1 UVLO0 VUVLO
0 0 2.5 V
0 1 2.75 V
1 0 3.0 V
1 1 3.25 V

Table 21. VMAIN Converter Output Voltage

MAIN1 MAIN0 VMAIN
0 0 2.5 V
0 1 2.75 V
1 0 3.0 V
1 1 3.3 V

7.5.13 VDCDC2 Register (offset: 0Dh) (reset: 60h/70h)

The VDCDC2 register is used to program the VCORE switching converter output voltage. It is programmable in 8 steps between 0.85 V and 1.8 V. The default value is governed by the DEFCORE pin; DEFCORE=0 sets an output voltage of 1.5 V. DEFCORE=1 sets an output voltage of 1.8 V.

Figure 50. VDCDC2 Register
7 6 5 4 3 2 1 0
LP_COREOFF CORE2 CORE1 CORE0 CORELP1 CORELP0 VIB CORE
DISCHARGE
R/W-0 R/W-1 R/W-1 R/W-DEFCORE R/W-1 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. VDCDC2 Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 LP_COREOFF R/W 0h

0h = VCORE converter is enabled in low power mode.

1h = VCORE converter is disabled in low power mode.

6-5 COREx R/W 1h Table 23 shows all possible values of VCORE. The default value can subsequently be overwritten through the serial interface after start-up.
4 CORE0 R/W DEFCORE Table 23 shows all possible values of VCORE. The default value can subsequently be overwritten through the serial interface after start-up.
3 CORELP1 R/W 1h CORELP1 and CORELP0 can be used to set the VCORE voltage in low power mode. In low power mode, CORE2 is effectively 0, and CORE1, CORE0 take on the values programmed at CORELP1 and CORELP0, default 10 giving VCORE = 1.1 V as default in low power mode. When low power mode is exited, VCORE reverts to the value set by CORE2, CORE1, and CORE0.
2 CORELP0 R/W 0h CORELP1 and CORELP0 can be used to set the VCORE voltage in low power mode. In low power mode, CORE2 is effectively 0, and CORE1, CORE0 take on the values programmed at CORELP1 and CORELP0, default 10 giving VCORE = 1.1 V as default in low power mode. When low power mode is exited, VCORE reverts to the value set by CORE2, CORE1, and CORE0.
1 VIB R/W 0h

0h = Disables the VIB output transistor

1h = Enables the VIB output transistor to drive the vibrator motor.

0 CORE
DISCHARGE
R/W 0h

0h = Disables the active discharge of the VCORE converter output.

1h = Enables the active discharge of the VCORE converter output in WAIT mode, or if VDCDC2 <7>= 1 in LOW POWER mode.

Table 23. VCORE Values

CORE2 CORE1 CORE0 VCORE
0 0 0 0.85 V
0 0 1 1.0 V
0 1 0 1.1 V
0 1 1 1.2 V
1 0 0 1.3 V
1 0 1 1.4 V
1 1 0 1.5 V
1 1 1 1.8 V

7.5.14 VREGS1 Register (offset: 0Eh) (reset: 88h)

The VREGS1 register is used to program and enable LDO1 and LDO2 and to set their behavior when low power mode is active. The LDO output voltages can be set either on the fly, while the relevant LDO is disabled, or simultaneously when the relevant enable bit is set. Note that both LDOs are per default ON.

Figure 51. VREGS1 Register
7 6 5 4 3 2 1 0
LDO2 enable LDO2 OFF/ nSLP LDO21 LDO20 LDO1 enable LDO1 OFF/ nSLP LDO11 LDO10
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. VREGS1 Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 LDO2 enable R/W 1h The function of the LDO2 enable and LDO2 OFF/nSLP bits is shown in Table 25. See the power-on sequencing section for details of low power mode.
6 LDO2 OFF / nSLP R/W 0h The function of the LDO2 enable and LDO2 OFF/nSLP bits is shown in Table 25. See the power-on sequencing section for details of low power mode.
5-4 LDO2x R/W 0h LDO2 has a default output voltage of 1.8 V. If desired, this can be changed at the same time as it is enabled through the serial interface. See Table 26.
3 LDO1 enable R/W 1h The function of the LDO1 enable and LDO1 OFF/nSLP bits is shown in Table 27. See the power-on sequencing section for details of low-power mode. Note that programming LDO1 to a higher voltage may force a system power-on reset if the increase is in the 10% or greater range.
2 LDO1 OFF / nSLP R/W 0h The function of the LDO1 enable and LDO1 OFF/nSLP bits is shown in Table 27. See the power-on sequencing section for details of low-power mode. Note that programming LDO1 to a higher voltage may force a system power-on reset if the increase is in the 10% or greater range.
1-0 LDO1x R/W 0h The LDO1 output voltage is per default set externally. If so desired, this can be changed through the serial interface. See Table 28.

Table 25. LDO2 Enable and LDO2 OFF/nSLP Functions

LDO2 ENABLE LDO2 OFF / nSLP LDO STATUS IN NORMAL MODE LDO STATUS IN LOW-POWER MODE
0 X OFF OFF
1 0 ON, full power ON, reduced power and performance
1 1 ON, full power OFF

Table 26. LDO21/LDO20

LDO21 LDO20 VLDO2
0 0 1.8 V
0 1 2.5 V
1 0 3.0 V
1 1 3.3 V

Table 27. LDO1 Enable and LDO1 OFF/nSLP Functions

LDO1 ENABLE LDO1 OFF / nSLP LDO STATUS IN NORMAL MODE LDO STATUS IN LOW-POWER MODE
0 X OFF OFF
1 0 ON, full power ON, reduced power and performance
1 1 ON, full power OFF

Table 28. LDO11/LDO10

LDO11 LDO10 VLDO1
0 0 ADJ
0 1 2.5 V
1 0 2.75 V
1 1 3.0 V

7.5.15 MASK3 Register (offset: 0Fh) (reset: 00h)

The MASK3 register must be considered when any of the GPIO pins are programmed as inputs.

Figure 52. MASK3 Register
7 6 5 4 3 2 1 0
Edge trigger GPIO4 Edge trigger GPIO3 Edge trigger GPIO2 Edge trigger GPIO1 Mask GPIO4 Mask GPIO3 Mask GPIO2 Mask GPIO1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. MASK3 Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-4 Edge trigger GPIOx R/W 0h

Determines whether the respective GPIO generates an interrupt at a rising or a falling edge.

0h = Falling edge triggered.

1h = Rising edge triggered.

3-0 Mask GPIOx R/W 0h Used to mask the corresponding interrupt. Default is unmasked (mask GPIOx = 0).

7.5.16 DEFGPIO Register (offset = 10h) (reset: 00h)

The DEFGPIO register is used to define the GPIO pins to be either input or output.

Figure 53. DEFGPIO Register
7 6 5 4 3 2 1 0
IO4 IO3 IO2 IO1 Value GPIO4 Value GPIO3 Value GPIO2 Value GPIO1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. DEFGPIO Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7-4 IOx R/W 0h

0h = Sets the corresponding GPIO to be an input.

1h = Sets the corresponding GPIO to be an output.

3-0 Value GPIOx R/W 0h

If a GPIO is programmed to be an output, then the signal output is determined by the corresponding bit. The output circuit for each GPIO is an open-drain NMOS requiring an external pullup resistor.

1h = Activates the relevant NMOS, hence forcing a logic low signal at the GPIO pin.

0h = Turns the open-drain transistor OFF, hence the voltage at the GPIO pin is determined by the voltage to which the pullup resistor is connected.

If a particular GPIO is programmed to be an input, then the contents of the relevant bit in B3-0 is defined by the logic level at the GPIO pin. A logic low forces a 0 and a logic high forces a 1. If a GPIO is programmed to be an input, then any attempt to write to the relevant bit in B3-0 is ignored.