SLVSAW1A June   2011  – January 2017 TPS65053-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Function
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Mode Selection
      2. 7.3.2 Enable
      3. 7.3.3 Reset
      4. 7.3.4 Short-Circuit Protection
      5. 7.3.5 Thermal Shutdown
        1. 7.3.5.1 Low Dropout Voltage Regulators
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Save Mode
        1. 7.4.1.1 Dynamic Voltage Positioning
        2. 7.4.1.2 Soft Start
        3. 7.4.1.3 100% Duty-Cycle Low Dropout Operation
        4. 7.4.1.4 Undervoltage Lockout
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Setting
        2. 8.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 8.2.2.2.1 Inductor Selection
          2. 8.2.2.2.2 Output Capacitor Selection
          3. 8.2.2.2.3 Input Capacitor Selection
        3. 8.2.2.3 Low Dropout Voltage Regulators (LDOs)
          1. 8.2.2.3.1 Input Capacitor and Output Capacitor Selection for the LDOs
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS65053-Q1 PMIC integrates two step-down converters and three LDOs which can be used to power the voltage rails needed by a processor or another application. The PMIC can be controlled via the ENABLE and MODE pins or sequenced from the VIN using RC delay circuits. There is a logic output, RESET, to provide the application processor or load a logic signal indicating power good or reset.

8.2 Typical Application

TPS65053-Q1 typ_app_lvs754.gif Figure 9. Typical Application Circuit

8.2.1 Design Requirements

Table 1 lists the design parameters for this application example.

Table 1. Power Design Requirements

PARAMETER VALUE
Buck 1 and 2 Input voltage, VINDCDC1/2 2.9 to 6 V (labeled Vbat in Figure 9)
Buck 1 Output voltage, VDCDC1 2.85 V (see Table 2 for FB_DCDC1 resistor divider selection)
Buck 1 Output current, IOUTDCDC1 1 A
Buck 2 Output voltage, VDCDC2 1.8 V (see Table 2 for FB_DCDC2 resistor divider selection)
Buck 2 Output current, IOUTDCDC2 600 mA
Linear Regulator 1 Input voltage, VINLDO1 2.85 V (from VDCDC1, as shown in Figure 9)
Linear Regulator 1 Output voltage, VLDO1 1.6 V (see Table 5 for FB_LDO1 resistor divider selection)
Linear Regulator 1 Output current, ILDO1 400 mA
Linear Regulator 2 and 3 Input voltage, VINLDO2/3 2.9 to 6 V (labeled Vbat in Figure 9)
Linear Regulator 2 Output voltage, VLDO2 3.3 V (see Table 5 for FB_LDO2 resistor divider selection)
Linear Regulator 2 Output current, ILDO2 200 mA
Linear Regulator 3 Output voltage, VLDO3 1.3 V (fixed)
Linear Regulator 3 Output current, ILDO3 200 mA

8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Setting

Use Equation 4 to calculate the output voltage of the DC-DC converters, with an internal reference voltage Vref, 0.6 V (typical). This voltage can be set by an external resistor network.

Equation 4. TPS65053-Q1 q4_vout_lvs754.gif

TI recommends setting the total resistance of R1 + R2 to less than 1 MΩ. The resistor network connects to the input of the feedback amplifier; therefore, requiring some small feed-forward capacitor in parallel to R1. A typical value of 47 pF is sufficient.

Equation 5. TPS65053-Q1 q5_r1_lvs754.gif

Table 2. Typical DC-DC Feedback Resistor Values

OUTPUT VOLTAGE R1 R2 NOMINAL VOLTAGE TYPICAL Cff
3.3 V 680 kΩ 150 kΩ 3.32 V 47 pF
3 V 510 kΩ 130 kΩ 2.95 V 47 pF
2.85 V 560 kΩ 150 kΩ 2.84 V 47 pF
2.5 V 510 kΩ 160 kΩ 2.51 V 47 pF
1.8 V 300 kΩ 150 kΩ 1.8 V 47 pF
1.6 V 200 kΩ 120 kΩ 1.6 V 47 pF
1.5 V 300 kΩ 200 kΩ 1.5 V 47 pF
1.2 V 330 kΩ 330 kΩ 1.2 V 47 pF

8.2.2.2 Output Filter Design (Inductor and Output Capacitor)

8.2.2.2.1 Inductor Selection

The two converters operate typically with a 2.2-μH output inductor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. For output voltages higher than 2.8 V, an inductor value of 3.3 μH minimum should be selected, otherwise the inductor current will ramp down too fast causing imprecise internal current measurement and therefore increased output voltage ripple under some operating conditions in PFM mode.

The selected inductor must be rated for its DC resistance and saturation current. The DC resistance of the inductance will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency.

Use Equation 6 to calculate the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 6. This is recommended because during heavy load transient the inductor current will rise above the calculated value.

Equation 6. TPS65053-Q1 q6_delta_lvs754.gif

where

  • f = Switching Frequency (2.25-MHz typical)
  • L = Inductor Value
  • Δ IL = Peak-to-peak inductor ripple current
  • ILmax = Maximum Inductor current

The highest inductor current occurs at the maximum VIN. Open core inductors have a soft saturation characteristic, and they can normally handle higher inductor currents versus a comparable shielded inductor.

A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. The fact that the core material from inductor to inductor differs and will have an impact on the efficiency especially at high switching frequencies must be considered. Refer to Table 3 and the typical applications for possible inductors.

Table 3. Tested Inductors

INDUCTOR TYPE INDUCTOR VALUE SUPPLIER
LPS3010 2.2 μH Coilcraft
LPS3015 3.3 μH Coilcraft
LPS4012 2.2 μH Coilcraft
VLF4012 2.2 μH TDK

8.2.2.2.2 Output Capacitor Selection

The advanced Fast Response voltage mode control scheme of the two converters allow the use of small ceramic capacitors with a typical value of 10 μF, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple and are therefore recommended. See the recommended components in Table 5.

If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application requirements. Use Equation 7 to calculate the rms ripple current.

Equation 7. TPS65053-Q1 q7_irmsc_lvs754.gif

At nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor as shown in Equation 8.

Equation 8. TPS65053-Q1 q8_deltav_lvs754.gif

Where the highest output voltage ripple occurs at the highest input voltage, VIN.

At light load currents, the converters operate in Power Save Mode and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.

8.2.2.2.3 Input Capacitor Selection

Because of the nature of the buck converter, having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. The converters need a ceramic input capacitor of 10 μF. The input capacitor can be increased without any limit for better input voltage filtering.

Table 4. Possible Capacitors for DC-DC Converters and LDOs

CAPACITOR VALUE SIZE SUPPLIER TYPE
2.2 μF 0805 TDK C2012X5R0J226MT Ceramic
2.2 μF 0805 Taiyo Yuden JMK212BJ226MG Ceramic
10 μF 0805 Taiyo Yuden JMK212BJ106M Ceramic
10 μF 0805 TDK C2012X5R0J106M Ceramic

8.2.2.3 Low Dropout Voltage Regulators (LDOs)

The output voltage of LDO1 and LDO2 can be set by an external resistor network and can be calculated as shown in Equation 9 with an internal reference voltage, Vref, typical 1 V.

Equation 9. TPS65053-Q1 q9_vout1_lvs754.gif

TI recommends setting the total resistance of R5 + R6 to less than 1 MΩ. Typically, no feedforward capacitor is required at the voltage dividers for the LDOs.

Equation 10. TPS65053-Q1 q10_vout2_lvs754.gif

Table 5. Typical LDO Feedback Resistor Values

OUTPUT VOLTAGE R5 R6 NOMINAL VOLTAGE
3.3 V 300 kΩ 130 kΩ 3.31 V
3 V 300 kΩ 150 kΩ 3 V
2.85 V 240 kΩ 130 kΩ 2.85 V
2.8 V 360 kΩ 200 kΩ 2.8 V
2.5 V 300 kΩ 200 kΩ 2.5 V
1.8 V 240 kΩ 300 kΩ 1.8 V
1.5 V 150 kΩ 300 kΩ 1.5 V
1.3 V 36 kΩ 120 kΩ 1.3 V
1.2 V 100 kΩ 510 kΩ 1.19 V
1.1 V 33 kΩ 330 kΩ 1.1 V

8.2.2.3.1 Input Capacitor and Output Capacitor Selection for the LDOs

The minimum input capacitor on VIN_LDO1 and on VIN_LDO2/3 is 2.2 μF minimum. LDO1 is designed to be stable with an output capacitor of 4.7 μF minimum; whereas, LDO2 and LDO3 are stable with a minimum capacitor value of 2.2 μF.

8.2.3 Application Curves

TPS65053-Q1 vo_rip_low_lvs754.gif
PWM/PFM Mode = Low
Figure 10. Output Voltage Ripple of DCDC1/2 in PFM Mode
TPS65053-Q1 dcdc1_startup_lvs754.gif Figure 12. DCDC1, DCDC2, LDO1 Startup Timing
TPS65053-Q1 dcdc1_load_hi_lvs710.gif Figure 14. DCDC1 Load Transient Response in PWM Mode
TPS65053-Q1 dcdc2_load_hi_lvs710.gif Figure 16. DCDC2 Load Transient Response in PWM Mode
TPS65053-Q1 dcdc1_line_hi_lvs710.gif Figure 18. DCDC1 Line Transient Response in PWM Mode
TPS65053-Q1 ldo1_load_lvs754.gif Figure 20. LDO1 Load Transient Response
TPS65053-Q1 ldo1_line_lvs710.gif Figure 22. LDO1 Line Transient Response
TPS65053-Q1 vo_rip_high_lvs754.gif
PWM Mode = High
Figure 11. Output Voltage Ripple of DCDC1/2 in
PWM Mode
TPS65053-Q1 ldo_startup_lvs754.gif Figure 13. LDO1 to LDO3 Startup Timing
TPS65053-Q1 dcdc1_load_low_lvs710.gif Figure 15. DCDC1 Load Transient Response in PFM Mode
TPS65053-Q1 dcdc2_load_low_lvs710.gif Figure 17. DCDC2 Load Transient Response in PFM Mode
TPS65053-Q1 dcdc2_line_hi_lvs710.gif Figure 19. DCDC2 Line Transient Response in PWM Mode
TPS65053-Q1 ldo3_load_lvs754.gif Figure 21. LDO3 Load Transient Response