JAJSK46A November   2020  – August 2021 TPS6521845

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     4
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 7.3.1.1  Power-Up Sequencing
        2. 7.3.1.2  Power-Down Sequencing
        3. 7.3.1.3  Strobe 1 and Strobe 2
        4. 7.3.1.4  Supply Voltage Supervisor and Power-Good (PGOOD)
        5. 7.3.1.5  Backup Supply Power-Good (PGOOD_BU)
        6. 7.3.1.6  Internal LDO (INT_LDO)
        7. 7.3.1.7  Current Limited Load Switches
          1. 7.3.1.7.1 Load Switch 1 (LS1)
          2. 7.3.1.7.2 Load Switch 2 (LS2)
          3. 7.3.1.7.3 Load Switch 3 (LS3)
        8. 7.3.1.8  LDO1
        9. 7.3.1.9  Coin Cell Battery Voltage Acquisition
        10. 7.3.1.10 UVLO
        11. 7.3.1.11 Power-Fail Comparator
        12. 7.3.1.12 Battery-Backup Supply Power-Path
        13. 7.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
        14. 7.3.1.14 I/O Configuration
          1. 7.3.1.14.1 Configuring GPO2 as Open-Drain Output
          2. 7.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
        15. 7.3.1.15 Push Button Input (PB)
          1. 7.3.1.15.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 7.3.1.15.2 Push Button Reset
        16. 7.3.1.16 AC_DET Input (AC_DET)
        17. 7.3.1.17 Interrupt Pin (INT)
        18. 7.3.1.18 I2C Bus Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
      2. 7.4.2 OFF
      3. 7.4.3 ACTIVE
      4. 7.4.4 SUSPEND
      5. 7.4.5 RESET
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Applications Without Battery Backup Supplies
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Filter Design
        2. 8.2.2.2 Inductor Selection for Buck Converters
        3. 8.2.2.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1.12 Battery-Backup Supply Power-Path

DCDC5 and DCDC6 are supplied from either the CC (coin-cell battery) input or IN_BU (main system supply). The power-path is designed to prioritize IN_BU to maximize coin-cell battery life. Whenever the PMIC is powered-up (WAIT_PWR_EN, ACTIVE, SUSPEND, and RECOVERY state), the power-path is forced to select the IN_BU input. In OFF mode the power-path selects the higher of the two inputs with a built-in hysteresis of 150 mV as shown in Figure 7-18.

GUID-A4547A4C-15FB-4B9D-B83B-105C817FD4FC-low.gifFigure 7-18 Switching Behavior of the Battery-Backup-Supply Power-Path; Power-Path Hysteresis
GUID-96425DAF-96C0-4FA7-B01B-60BBB9791549-low.gif
A. System is supplied by Li-Ion battery with a fresh coin-cell backup battery.
B. (VIN_BIAS slow decay)
Figure 7-20 Switching Behavior of the Battery-Backup-Supply Power-Path; Weakening Main Battery, Strong Coin-Cell
GUID-6E089C37-32FE-4695-A38C-19F97AE0207C-low.gif
A. Main Supply is disconnected or decays rapidly.
B. Rapid decay of VIN_BIAS (preregulator)
Figure 7-19 Switching Behavior of the Battery-Backup-Supply Power-Path; Main Power Supply Removal
GUID-7F47B3F3-7BA5-4825-AA03-11E8207719D3-low.gif
A. System is supplied by Li-Ion battery with a weak coin-cell backup battery.
B. VIN_BIAS slow decay
Figure 7-21 Switching Behavior of the Battery-Backup-Supply Power-Path; Weakening Main Battery, Weak Coin-Cell

When VIN_BIAS drops below the UVLO threshold, the PMIC shuts down all rails and enters OFF mode. At this point the power-path selects the higher of the two input supplies. If the coin-cell battery is less than 150 mV above the UVLO threshold, SYS_BU remains connected to IN_BU (see Figure 7-20). If the coin-cell is >150 mV above the UVLO threshold, the power-path switches to the CC input as shown in Figure 7-21. With no load on the main supply, the input voltage may recover over time to a value greater than the coin-cell voltage and the power-path switches back to IN_BU. This is a typical behavior in a Li-Ion battery powered system.

Depending on the system load, VIN_BIAS may drop below VINT_LDO before the power-down sequence is completed. In that case, INT_LDO is turned OFF and the digital core is reset forcing the unit into OFF mode and the power-path switches to IN_BU as shown in Figure 7-19.