JAJSQ72B june   2014  – may 2023 TPS65262-1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjusting the Output Voltage
      2. 8.3.2  Enable and Adjusting UVLO
      3. 8.3.3  Soft-Start Time
      4. 8.3.4  Power-Up Sequencing
        1. 8.3.4.1 External Power Sequencing
        2. 8.3.4.2 Automatic Power Sequencing
      5. 8.3.5  V7V Low Dropout Regulator and Bootstrap
      6. 8.3.6  Out-of-Phase Operation
      7. 8.3.7  Output Overvoltage Protection (OVP)
      8. 8.3.8  PSM
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Overcurrent Protection (OCP)
        1. 8.3.10.1 High-Side MOSFET OCP
        2. 8.3.10.2 Low-Side MOSFET OCP
      11. 8.3.11 Power Good
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 4.5 V (Minimum VIN)
      2. 8.4.2 Operation With EN Control
      3. 8.4.3 Operation at Light Loads
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Loop Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.11 Power Good

The PGOOD pin is an open-drain output. When feedback voltage of each buck is between 95% (rising) and 105% (falling) of the internal voltage reference, the PGOOD pin pulldown is deasserted and the pin floats. TI recommends to use a pullup resistor between the values of 10 to 100 kΩ to a voltage source that is 6.3 V or less. The PGOOD is in a defined state when the VIN input voltage is greater than 1 V but with reduced current sinking capability. The PGOOD achieves full current sinking capability when the VIN input voltage is above UVLO threshold, which is 4.25 V typically.

The PGOOD pin is pulled low when any feedback voltage of buck is lower than 92.5% (falling) or greater than 107.5% (rising) of the nominal internal reference voltage. Also, the PGOOD is pulled low, if the input voltage is undervoltage locked up, thermal shutdown is asserted, the EN pin is pulled low or the converter is in a soft-start period.