SLVSCW2A September   2015  – February 2016 TPS657095

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  State Diagram
      2. 7.3.2  Power-up Timing
      3. 7.3.3  GPO
      4. 7.3.4  GPIO
      5. 7.3.5  LED_EN
      6. 7.3.6  PWM Dimming
      7. 7.3.7  Crystal Oscillator and CLKOUT
      8. 7.3.8  LDOs
      9. 7.3.9  Undervoltage Lockout
      10. 7.3.10 Power Up/Power Down Default States
      11. 7.3.11 Output Voltage Discharge for LDO1 and LDO2
      12. 7.3.12 Power-Good Status Bits for LDO1 and LDO2
      13. 7.3.13 Short-Circuit Protection
      14. 7.3.14 Thermal Shutdown
      15. 7.3.15 LED Driver
      16. 7.3.16 4kByte OTP Memory
        1. 7.3.16.1 Programming the 4KByte OTP Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Operational Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Map
      1. 7.6.1  DEV_AND_REV_ID Register Address: 00h
      2. 7.6.2  OTP_REV Register Address: 01h
      3. 7.6.3  GPIO_CTRL Register Address: 02h
      4. 7.6.4  PWM_OSC_CNTRL Register Address: 03h
      5. 7.6.5  ISINK_CURRENT Register Address: 04h
      6. 7.6.6  LDO_CTRL Register Address: 05h
      7. 7.6.7  LDO1_VCTRL Register Address: 06h
      8. 7.6.8  LDO2_VCTRL Register Address: 07h
      9. 7.6.9  PWM_DUTY_THR_L Register Address: 08h
      10. 7.6.10 PWM_DUTY_THR_H Register Address: 09h
      11. 7.6.11 RESERVED Register Address: 0Ah
      12. 7.6.12 PWM_DUTY_L Register Address: 0Bh
      13. 7.6.13 PWM_DUTY_H Register Address: 0Ch
      14. 7.6.14 RESERVED Register Address: 0Dh
      15. 7.6.15 SPARE Register Address: 0Eh
      16. 7.6.16 4K_OTP_PASSWORD Register Address: 0Fh
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Capacitor Selection
        2. 8.2.2.2 Input Capacitor Selection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Summary
    2. 12.2 Chip Scale Package Dimensions

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発注情報

7 Detailed Description

7.1 Overview

The TPS657095 integrates two LDOs, a PWM-dimmable current sink for driving an LED, one GPIO for controlling an external device and one GPO for controlling an embedded camera module.

7.2 Functional Block Diagram

TPS657095 Block_Diagram_TPS.gif

7.3 Feature Description

7.3.1 State Diagram

The state diagram below details the basic operation of this device.

TPS657095 State_Diagram.gif Figure 6. State Diagram

7.3.2 Power-up Timing

The timing diagram below details the state of the input signals and output voltages in a power-up event.

TPS657095 Timing.gif Figure 7. Power-Up Timing

7.3.3 GPO

The TPS657095 has one general purpose output (GPO) that can be used to control a camera image sensor. Bit 0 of the GPIO_CTRL Register can be used to set the output level and bit 1 of the GPIO_CTRL Register can be used to define whether the output is an open-drain or push-pull output. Internally, the GPO output buffer is connected to LDO1. Therefore, LDO1 has to be enabled in order for the GPO output to operate. In the open-drain configuration, the external pull-up resistor should be pulled up to a voltage that is equal to or less than VCC at all times. Connecting the pull-up resistor to a voltage source that is greater than VCC or present whenever VCC is not present may cause an unwanted leakage path.

7.3.4 GPIO

The TPS657095 has one general purpose input/output (GPIO) that can be used to control an external device when configured as an output. When configured as an input, the GPIO pin serves as a dedicated LDO2 enable. This discrete pin is 'ORed' with the software LDO2 enable. The functionality is shown in the following table.

Table 1. LDO2 Output Control

GPIO (configured as an input) EN_LDO2 (bit 1 of the LDO_CTRL REGISTER LDO2 OUTPUT
0 0 Off
0 1 On
1 0 On
1 1 On

The GPIO_CTRL register contains the bits used to configure this GPIO. Bit 3 of the GPIO_CTRL Register can be used to set the output level, bit 4 can be used to configure the GPIO as an input or an output, and bit 5 of the GPIO_CTRL Register can be used to define whether the output is an open-drain or push-pull output. Internally, the GPIO output buffer is connected to LDO1. Therefore, LDO1 has to be enabled in order for the GPIO to operate. In the open-drain configuration, the external pull-up resistor should be pulled up to a voltage that is equal to or less than VCC at all times. Connecting the pull-up resistor to a voltage source that is greater than VCC or present whenever VCC is not present may cause an unwanted leakage path.

7.3.5 LED_EN

The TPS657095 has a pin, LED_EN, which is used to control a privacy LED. The privacy LED can only be turned on or off using the LED_EN pin. No other means to control the privacy LED exists in this device. The LED driver circuit of this device is internally biased by an internal 1.8V reference which is automatically powered once a valid voltage is present on the VCC/AVCC pins of this device. The input leakage current specified in the Electrical Characteristics section of this datasheet will not be exceeded even if a logic high voltage is applied to this pin while VCC/AVCC are not present.

7.3.6 PWM Dimming

LED_EN serves as the enable for the internal PWM.

  • LED_EN = 0: LED is OFF
  • LED_EN = 1: LED is ON / internal PWM is enabled

Since the crystal oscillator is needed for the internal PWM dimming, it is automatically enabled based on the status of the LED_EN pin and on the CLKout_EN register bit.

CLKout_EN LED_EN ISINK CRYSTAL OSCILLATOR ENABLED
CLKout
0 0 OFF OFF OFF
0 1 ON - internal PWM ON OFF
1 0 OFF ON ON
1 1 ON - internal PWM ON ON

7.3.7 Crystal Oscillator and CLKOUT

The crystal oscilaltor is used to provide a clock signal to the camera image sensor via the CLKOUT pin. It is also used to control the internal PWM for dimming the LED. The crystal oscillator is enabled by either the CLKout_EN bit in the PWM_OSC_CNTRL register or by driving the LED_EN pin to a high state.

The CLKOUT buffer is internally supplied by LDO1, hence LDO1 needs to be enabled for proper functionality of the clock output. the CLKOUT buffer is enabled only when bit 2 of the PWM_OSC_CNTRL Register is set to a logic one. If bit 2 of the PWM_OSC_CNTRL register is set to a logic one while LDO1 is disabled, the crystal oscillator will run but the clock output will not be present on the CLKOUT pin. The OSC_FREQ[1:0] bits in the PWM_OSC_CNTRL Register should be set prior to enabling the CLKOUT buffer.

In addition, the crystal oscillator is driving the internal charge pump that generates the programming voltage for the 4kByte OTP memory. For programming the OTP, the oscillator has to be enabled by setting CLKout_EN to a logic '1' at least 10ms before the OTP is written to allow the crystal to stabilize.

The oscillator circuit used does not require external components other than the crystal itself on pins XI and XO. Internally, the oscillator circuit contains two 16pF capacitors connected from XI to GND and from XO to GND. It is designed for an equivalent series resistance of the crystal to be less than 100Ω. Therefore, a crystal must be used with a series resistance of less than this value and no other resistors in series or in parallel to the crystal must be added.

The signal on CLKOUT is delayed from the CLKout_EN bit enabling the output buffer until the oscillator is stable. Once it has stabilized, an additional internal wait time of 131072 clk cycles x 1/24MHz has been added internally to the design before the output is set active. Given the typical start-up time of the crystal oscillator, it is safe to assume the total start-up time which depends on the crystal used including the 131072 cycles of clk delay is less than 10ms.

Table 2. Tested Crystals

TYPE NOMINAL FREQUENCY LOAD CAPACITANCE EQUIVALENT SERIES RESISTANCE SUPPLIER
8Q-24.000MEEV-T 24MHz 8pF (16pF on each pin) 100Ω maximum TXC

7.3.8 LDOs

The low dropout voltage regulators are designed to operate with low value ceramic input and output capacitors. Both LDOs contain a current limit feature which is used at start up to control the voltage ramp time.

LDO1 is enabled by bit 0 of the LDO_CTRL register. LDO2 can be enabled by either bit 1 of the LDO_CTRL register or by the GPIO if configured as an input. Since the input buffer for the GPIO is powered by LDO1, LDO1 must be enabled before the GPIO pin can be used to enable LDO1. In the case of a thermal event, the register enable bits will be cleared with no auto-re-start feature so as to allow the application software to control the power sequencing of the LDOs.

7.3.9 Undervoltage Lockout

The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. It disables the complete device at low input voltages.

The supply voltage to the TPS657095 is internally sensed at pin AVCC. When the voltage at AVCC exceeds the UVLO limit, the internal enable signals turns HIGH and allows the device to operate. When the supply voltage drops below the UVLO limit, TPS657095 is forced OFF, all functions are disabled and the LDO output voltage discharge circuitry is forced ON to ramp down the output voltage. However, if the input voltage drops below 2V, the discharge circuit becomes inactive.

7.3.10 Power Up/Power Down Default States

The GPO, GPIO and CLKOUT pins contain internal buffers powered by LDO1. The following table shows their state during a power up (UVLO Rising) and power down (UVLO Falling) event.

Table 3. Power Up/Power Down Events

CIRCUIT EVENT
VCC > UVLO, LDO1 TURN-OFF VCC RISING > UVLO, LDO1 IN AN 'OFF' STATE VCC > UVLO, LDO1 TURN-ON VCC FALLING < UVLO, LDO1 IN AN 'OFF' STATE
GPO Off (1) Off (1) Push-Pull, Low Level Off (1)
GPIO Off (1)(2) Off (1)(2) Input (3) Off (1)
Register Bits no change OTP Load State no change Reset State
CLKOUT Off (1) Off (1) Low (CLKOUT_EN = low) Off (1)
(1) Output is 'off' as a result of no power supply. The output follows LDO1 to within a diode drop.
(2) The GPIO_STATE bit (bit 3 in the GPIO_CTRL register) is forced to a logic low.
(3) The default setting is configured as an input. This can be modified by using the GPIO_CTRL register.

7.3.11 Output Voltage Discharge for LDO1 and LDO2

The LDOs contain an output capacitor discharge feature which makes sure that the capacitor is discharged to GND when the supply voltage drops below the undervoltage lockout threshold. The discharge function is enabled when voltage is applied at AVCC starting at about 2.1V until the LDOs are enabled.

7.3.12 Power-Good Status Bits for LDO1 and LDO2

Bits PGOOD_LDO1 and PGOOD_LDO2 in register LDO_CTRL are driven by an comparator inside the LDOs to indicate when the output voltage is in regulation. The Bits are set 'high' when the LDO is in regulation. When the LDO is enabled but the voltage is not above the power-good threshold, the bit is set to a 'low' state. The bit is also set to a 'low' state if the LDO is disabled.

7.3.13 Short-Circuit Protection

All outputs are short circuit protected with a maximum output current as defined in the electrical specifications.

7.3.14 Thermal Shutdown

As soon as the junction temperature, TJ, exceeds 150°C (typically) for any of the LDOs, the LDO will go into thermal shutdown. In this case, the LDOs are turned-off. After the temperature has fallen below the threshold, the LDO remains off until it is enabled again by the I2C interface. There is no automatic power-on feature once the thermal event is past.

7.3.15 LED Driver

The TPS657095 contains a LED driver for a current of up to 30mA. ISINK is an open drain current sink that regulates a current in a LED. The anode of the LED needs to be tied to a positive supply voltage e.g., VCC or any other voltage within the limits of the electrical spec of TPS657095, depending on the forward voltage of the LED. The cathode of the LED is connected to ISINK which sets a constant current to GND. ISINK is regulated internally based on the default current set internally. If the LED_EN pin is pulled LOW, the LED driver is disabled and its output ISINK is high resistive. If LED_EN is HIGH, the current sink regulates to the current defined by the setting in the ISINK_CURRENT Register.

The internal PWM generator allows for internal dimming with a frequency of 3kHz, 6kHz, 12kHz or 24kHz. A 10Bit duty cycle register allows to set the duty cycle in a range from 0% to 99.9% using 8Bits PWM resolution and another 2Bits of dithering.

A signal applied at the LED_EN pin is used to synchronously enable and disable the internal PWM signal.

7.3.16 4kByte OTP Memory

The TPS657095 contains 4kBytes of one-time-programmable (OTP) memory to store user data. The memory has a linear address range from 0x0000 to 0x0FFF and uses two Byte addressing as described in the serial interface description. Reading beyond the specified linear address range will result in reading all zeros. Writes to an address space beyond the specified linear address range are inhibited.

The 4kByte OTP memory requires a programming voltage higher than 5V. The program voltage is generated internally by a charge pump which uses the VCC voltage as its input. During programming, Vcc has to be kept at 5V +/-5% (a voltage of 5.25V is recommended) and the internal oscillator has to be enabled 10ms before programming to allow the 24MHz crystal to stabilize. The 24MHz clock is needed for the internal charge pump to generate the programming voltage from Vcc.

As an added security measure, programming the 4kByte OTP memory requires a two byte sequential password to be written to in the PMU register space at address 0x0F. The two bytes must be written back to back with no restriction on the delay between the writes. Any data written at address 0x0F that does not match the password and sequence will disable the ability to program the 4kByte OTP memory.

7.3.16.1 Programming the 4KByte OTP Memory

1. Apply 5V +/-5% to the VCC and AVCC pins.

2. Enable the internal oscillator by driving the LED_EN pin to a high state or setting the CLKout_EN bit to a '1'.

3. Wait at least 10ms for the crystal to stabilize.

3. Using the PMU register I2C address, write the password to the 4K_OTP_PASSWORD register.

4. Using the 4kByte OTP memory I2C address, write the desired value to a specific address using the protocol shown in Figure 6.

5. Exit the programming of the 4KByte OTP memory by over writing the 4K_OTP_PASSWORD register with an incorrect password or by removing power to the device.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

The TPS657095 is in a 'Shutdown' mode if the voltage on the AVCC pin is below 1.8V. In this mode, the device will not respond to I2C commands nor will the LED_EN pin be operational.

7.4.2 Operational Mode

The TPS657095 enters an 'Operational' mode mode once a voltage greater than the UVLO limit is present on both the VCC and AVCC pins. In this mode, the I2C is active, the operation of the LED is controllable via the LED_EN pin and the LDOs can be enabled.

NOTE

The voltage on the AVCC and VCC pins should not be left in a state between the Shutdown Mode voltage and the Operational Mode voltage. Keeping the input voltage to the device in this indeterminate state will result in unwanted quiescent current consumption.

7.5 Programming

7.5.1 Serial Interface

The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above the UVLO threshold. The I2C interface is running from an internal oscillator that is automatically enabled when there is an access to the interface. Additional features supported by the I2C compatible interface are:

  • multi-byte read/write capability
  • clock stretching; specifically needed during OTP write

The 7bit device address for TPS657095 is:

  • "100 1000" for the PMU user registers
  • "101 1000" for the 4kByte OTP memory

For the PMU, at address "100 1000", the device address is followed by the 1Byte register address and 1Byte data (for a write instruction)

For the 4kByte OTP memory, at address "101 1000", the device address is followed by the 1Byte register address [7:0] followed by the second address Byte [15:8] and 1Byte data (for a write instruction) giving a 4kByte linear address range for the memory. Please note that the supply voltage range at pins VCC and AVCC during programming (writing) of the OTP memory is limited to 5V ±5%.

Attempting to read data from register addresses not listed in this section will result in 00h being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS657095 generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS657095 must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave device TPS657095 must leave the data line high to enable the master to generate the stop condition.

The interface is reset by the internal UVLO signal of TPS657095 or by a STOP condition. If the SCL and SDA signal is not stable at the time the UVLO threshold on pin Vcc is exceeded, the first communication may not be acknowledged and will have to be re-transmitted after a STOP condition.

Upon the application of power on the VCC/AVCC pins, the internal I2C buffers may sequence up in a manner that produces a false START. If a false START is detected, an internal synchronization clock will be enabled until a STOP condition is received. During the time that the internal synchronization clock is active, the device will consume an additional 120µA of current.

TPS657095 I2C_start_stop.gif Figure 8. START and STOP Conditions
TPS657095 I2C_if_write_lvscu4.gif Figure 9. Serial Interface WRITE to TPS657095 User Registers
TPS657095 I2C_if_read_lvscu4.gif Figure 10. Serial Interface READ from TPS657095 User Registers
TPS657095 I2C_OTP_write_lvscu4.gif Figure 11. Serial Interface WRITE to TPS657095 OTP Memory
TPS657095 I2C_OTP_read_lvscu4.gif Figure 12. Serial Interface READ from TPS657095 OTP Memory
TPS657095 I2C_bittransfer.gif Figure 13. Bit Transfer on the Serial Interface
TPS657095 I2C_acknowledge.gif Figure 14. Acknowledge on the I2C Bus
TPS657095 I2C_busprotocol.gif Figure 15. Bus Protocol

7.6 Register Map

7.6.1 DEV_AND_REV_ID Register Address: 00h

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Figure 16. DEV_AND_REV_ID Register
DEV_AND_REV_ID B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function DEV_ID[3] DEV_ID[2] DEV_ID[1] DEV_ID[0] REV_ID[3] REV_ID[2] REV_ID[1] REV_ID[0]
Default 0 1 0 1 0 1 0 0
Default set by: OTP OTP OTP OTP OTP OTP OTP OTP
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only;

Table 4. DEV_AND_REV_ID Field Descriptions

Bit Field Type Reset Description
Bit 7:4 DEV_ID[3:0] R 0101 Device ID: TPS657095 = 0101
Bit 3:0 REV_ID[3:0] R 0100 Die Revision ID: PG1.0 = 0100

7.6.2 OTP_REV Register Address: 01h

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Figure 17. OTP_REV Register Address: 01h Register
OTP_REV B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function RSVD OTP_REV[6] OTP_REV[5] OTP_REV[4] OTP_REV[3] OTP_REV[2] OTP_REV[1] OTP_REV[0]
Default 0 1 0 0 0 0 0 0
Default set by: OTP OTP OTP OTP OTP OTP OTP OTP
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only;

Table 5. OTP_REV Register Address: 01h Register Field Descriptions

Bit Field Type Reset Description
Bit 7 RSVD R 0
Bit 6:0 OTP_REV[6:0] R 1000000
Reserved: 100_0000: Production PG1.0 programming

7.6.3 GPIO_CTRL Register Address: 02h

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Figure 18. GPIO_CTRL Register
GPIO_CTRL B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function SPARE SPARE GPIO_driver GPIO_DIR GPIO_STATE SPARE GPO_driver GPO
Default 0 0 1 1 1 0 0 0
Defualt set by: OTP OTP OTP OTP OTP OTP OTP OTP
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R/W R/W R/W R R/W R/W
LEGEND: R/W = Read/Write; R = Read only;

Table 6. GPIO_CTRL Register Field Descriptions

Bit Field Type Reset Description
Bit 7:6 SPARE R 00
Bit 5 GPIO_driver R/W 1 0 = GPIO is configured as push pull output; internally connected to LDO1
1 = GPIO is configured as open drain output
Bit 4 GPIO_DIR R/W 1 0 = GPIO is configured as an input and used to enable LDO2
1 = GPIO is configured as an output
Bit 3 GPIO_STATE R/W 1 0 = actively pulled low
1 = high impedance output if the GPIO_driver bit is configured as an open-drain output / internally pulled up to the LDO1 voltage setting if the GPIO_driver bit is configured as a push-pull output
Bit 2 SPARE R 0
Bit 1 GPO_driver R/W 0 0 = GPO is configured as push pull output; internally connected to LDO1
1 = GPO is configured as open drain output
Bit 0 GPO R/W 0 0 = actively pulled low
1 = high impedance output if the GPO_driver bit is configured as an open-drain output / internally pulled up to the LDO1 voltage setting if the GPO_driver bit is configured as a push-pull output

7.6.4 PWM_OSC_CNTRL Register Address: 03h

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Figure 19. PWM_OSC_CNTRL Register
OSCILLATOR_CONTROL B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function SPARE SPARE SPARE PWM_
FREQ[1]
PWM_
FREQ[0]
CLKout_EN OSC_FREQ[1] OSC_FREQ[0]
Default 0 0 0 1 1 0 0 0
Default set by: OTP OTP OTP OTP OTP OTP OTP OTP
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only;

Table 7. PWM_OSC_CNTRL Register Field Descriptions

Bit Field Type Reset Description
Bit 7:5 SPARE R 000
Bit 4:3 PWM_FREQ[1:0] R/W 11 Frequency divider for internally generated PWM signal:
00 : f(PWM) = 23.5KHz
01 : f(PWM) = 11.7KHz
10 : f(PWM) = 5.8KHz
11 : f(PWM) = 2.9KHz
Bit 2 CLKout_EN R/W 0 0 = CLKOUT is disabled and the output is held LOW
1 = the crystal oscillator is forced ON; CLKOUT is enabled and is switching with the frequency defined by OSC_FREQ[1..0]; LDO1 needs to be enabled for CLKout being active
Please note that the crystal oscillator itself is active once the Bit is set high, independently of the status of LDO1.
Bit 1:0 OSC_FREQ[1:0] R/W 00 Frequency divider for CLKOUT generated from 24MHz crystal)
00 : f(CLKOUT) = f(OSC) = 24MHz
01 : f(CLKOUT) = f(OSC) / 2 = 12MHz
10 : f(CLKOUT) = f(OSC) / 4 = 6MHz
11 : f(CLKOUT) = f(OSC) / 8 = 3MHz

7.6.5 ISINK_CURRENT Register Address: 04h

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Figure 20. ISINK_CURRENT Register
ISINK_CURRENT B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function SPARE SPARE SPARE ISINK[4] ISINK[3] ISINK[2] ISINK[1] ISINK[0]
Default 0 0 0 0 1 0 0 0
Default set by: OTP OTP OTP OTP OTP OTP OTP OTP
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only;

Table 8. ISINK_CURRENT Register Field Descriptions

Bit Field Type Reset Description
Bit 7:5 SPARE R 000
Bit 4:0 ISINK[4:0] R 01000 ISINK dc current setting


TPS657095: Factory programmed to 5'b01000 (10mA)

7.6.6 LDO_CTRL Register Address: 05h

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Figure 21. LDO_CTRL Register
LDO_CTRL B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function SPARE SPARE PGOOD_LDO2 PGOOD_LDO1 SPARE SPARE EN_LDO2 EN_LDO1
Default 0 0 - - 0 0 0 0
Default set by: OTP OTP OTP OTP OTP OTP OTP OTP
Default value loaded by: UVLO UVLO PGOOD of LDO2 PGOOD of LDO1 UVLO UVLO UVLO UVLO
Read/write R R R R R R R/W R/W
LEGEND: R/W = Read/Write; R = Read only;

Table 9. LDO_CTRL Register Field Descriptions

Bit Field Type Reset Description
Bit 7:6 SPARE R 00
Bit 5 PGOOD LDO2 R Power good status Bit for LDO2 (power good threshold relative to target value: 95% rising and 90% falling)
0 = the output voltage of LDO2 is below the power good threshold or LDO2 is disabled; default value as LDO2 is disabled by default
1 = the output voltage of LDO2 is above the power good threshold
Bit 4 PGOOD LDO1 R Power good status Bit for LDO1 (power good threshold relative to target value: 95% rising and 90% falling)
0 = the output voltage of LDO1 is below the power good threshold or LDO1 is disabled; default value as LDO1 is disabled by default
1 = the output voltage of LDO1 is above the power good threshold
Bit 3 NC: R 0
Bit 2 SPARE R 0
Bit 1 EN_LDO2 R/W 0 0 = LDO2 is disabled (Default: TPS657095)
1 = LDO2 is enabled
Bit 0 EN_LDO1 R/W 0 0 = LDO1 is disabled (Default: TPS657095)
1 = LDO1 is enabled

7.6.7 LDO1_VCTRL Register Address: 06h

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Figure 22. LDO1_VCTRL Register
LDO1_VCTRL B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function SPARE SPARE LDO1[5] LDO1[4] LDO1[3] LDO1[2] LDO1[1] LDO1[0]
Default 0 0 1 0 0 1 0 0
Default set by: OTP OTP OTP OTP OTP OTP OTP OTP
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only;

Table 10. LDO1_VCTRL Register Field Descriptions

Bit Field Type Reset Description
Bit 7:6 SPARE R 00
Bit 5:0 LDO1[5:0] R/W 100100 Output voltage setting for LDO1(1)(2)
(1) A Voltage change during operation must not exceed 8% of the value set in the register for each I2C write access as this may trigger the internal power good comparator and will trigger the Reset of the device. This limitation is only for a voltage step to higher voltages. There is no limitation for programming lower voltages by I2C.
(2) The output voltage setting cannot be changed if the LOCK_BIT in the OTP_REV_LOCK_BIT register is set to a logic '1'.

7.6.8 LDO2_VCTRL Register Address: 07h

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Figure 23. LDO2_VCTRL Register
LDO2_VCTRL B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function SPARE SPARE LDO2[5] LDO2[4] LDO2[3] LDO2[2] LDO2[1] LDO2[0]
Default 0 0 0 1 0 0 0 0
Default set by: OTP OTP OTP OTP OTP OTP OTP OTP
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only;

Table 11. LDO2_VCTRL Field Descriptions

Bit Field Type Reset Description
Bit 7:6 SPARE R 00
Bit 5:0 LDO2[5:0] R/W 010000 Output voltage setting for LDO2(1)(2)
(1) A Voltage change during operation must not exceed 8% of the value set in the register for each I2C write access as this may trigger the internal power good comparator and will trigger the Reset of the device. This limitation is only for a voltage step to higher voltages. There is no limitation for programming lower voltages by I2C.
(2) The output voltage setting cannot be changed if the LOCK_BIT in the OTP_REV_LOCK_BIT register is set to a logic '1'.
OUTPUT VOLTAGE [V] B5 B4 B3 B2 B1 B0
0 0.800 0 0 0 0 0 0
1 0.825 0 0 0 0 0 1
2 0.850 0 0 0 0 1 0
3 0.875 0 0 0 0 1 1
4 0.900 0 0 0 1 0 0
5 0.925 0 0 0 1 0 1
6 0.950 0 0 0 1 1 0
7 0.975 0 0 0 1 1 1
8 1.000 0 0 1 0 0 0
9 1.025 0 0 1 0 0 1
10 1.050 0 0 1 0 1 0
11 1.075 0 0 1 0 1 1
12 1.100 0 0 1 1 0 0
13 1.125 0 0 1 1 0 1
14 1.150 0 0 1 1 1 0
15 1.175 0 0 1 1 1 1
16 1.200 0 1 0 0 0 0
17 1.225 0 1 0 0 0 1
18 1.250 0 1 0 0 1 0
19 1.275 0 1 0 0 1 1
20 1.300 0 1 0 1 0 0
21 1.325 0 1 0 1 0 1
22 1.350 0 1 0 1 1 0
23 1.375 0 1 0 1 1 1
24 1.400 0 1 1 0 0 0
25 1.425 0 1 1 0 0 1
26 1.450 0 1 1 0 1 0
27 1.475 0 1 1 0 1 1
28 1.500 0 1 1 1 0 0
29 1.525 0 1 1 1 0 1
30 1.550 0 1 1 1 1 0
31 1.575 0 1 1 1 1 1
32 1.600 1 0 0 0 0 0
33 1.650 1 0 0 0 0 1
34 1.700 1 0 0 0 1 0
35 1.750 1 0 0 0 1 1
36 1.800 1 0 0 1 0 0
37 1.850 1 0 0 1 0 1
38 1.900 1 0 0 1 1 0
39 1.950 1 0 0 1 1 1
40 2.000 1 0 1 0 0 0
41 2.050 1 0 1 0 0 1
42 2.100 1 0 1 0 1 0
43 2.150 1 0 1 0 1 1
44 2.200 1 0 1 1 0 0
45 2.250 1 0 1 1 0 1
46 2.300 1 0 1 1 1 0
47 2.350 1 0 1 1 1 1
48 2.400 1 1 0 0 0 0
49 2.450 1 1 0 0 0 1
50 2.500 1 1 0 0 1 0
51 2.550 1 1 0 0 1 1
52 2.600 1 1 0 1 0 0
53 2.650 1 1 0 1 0 1
54 2.700 1 1 0 1 1 0
55 2.750 1 1 0 1 1 1
56 2.800 1 1 1 0 0 0
57 2.850 1 1 1 0 0 1
58 2.900 1 1 1 0 1 0
59 2.950 1 1 1 0 1 1
60 3.000 1 1 1 1 0 0
61 3.100 1 1 1 1 0 1
62 3.200 1 1 1 1 1 0
63 3.300 1 1 1 1 1 1

7.6.9 PWM_DUTY_THR_L Register Address: 08h

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Figure 24. PWM_DUTY_THR_L Register
PWM_DUTY_THR_L B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function PWM_DC_TH[7] PWM_DC_TH[6] PWM_DC_TH[5] PWM_DC_TH[4] PWM_DC_TH[3] PWM_DC_TH[2] PWM_DC_TH[1] PWM_DC_TH[0]
Default 1 1 1 1 1 1 1 1
Default set by: OTP OTP OTP OTP OTP OTP OTP OTP
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only;

Table 12. PWM_DUTY_THR_L Register Field Descriptions

Bit Field Type Reset Description
Bit 7:0 PWM_DC_TH[7:0] R 11111111 Lower 8 bits of PWM duty cycle threshold for internally generated PWM on ISINK(1)
(1) The contents of the PWM_DUTY_THR_L register is factory programmed and read only.

7.6.10 PWM_DUTY_THR_H Register Address: 09h

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Figure 25. PWM_DUTY_THR_H Register
PWM_DUTY_THR_H B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function PWM_DC_TH[9] PWM_DC_TH[8]
Default 0 0 0 0 0 0 0 0
Default set by: OTP OTP OTP OTP OTP OTP OTP OTP
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only;

Table 13. PWM_DUTY_THR_H Register Field Descriptions

Bit Field Type Reset Description
Bit 7:0 PWM_DC_TH[7:0] R 00000000 Higher 2 Bits of PWM duty cycle threshold for internally generated PWM on ISINK Any attempt to write a lower value into PWM_DUTY than defined in PWM_DUTY_THR will be ignored.(1)
PWM_DC_TH[9:0] R 00000000 000h = 0% duty cycle
3FFh = 99.9% duty cycle
(1) The contents of the PWM_DUTY_THR_H register is factory programmed and read only.

7.6.11 RESERVED Register Address: 0Ah

Reserved

7.6.12 PWM_DUTY_L Register Address: 0Bh

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Figure 26. PWM_DUTY_L Register
PWM_DUTY_L B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function PWM
_DC[7]
PWM
_DC[6]
PWM
_DC[5]
PWM
_DC[4]
PWM
_DC[3]
PWM
_DC[2]
PWM
_DC[1]
PWM
_DC[0]; LSB
Default see (1) see (1) see (1) see (1) see (1) see (1) see (1) see (1)
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only;

Table 14. PWM_DUTY_L Register Field Descriptions

Bit Field Type Reset Description
Bit 7:0 PWM_DC[7:0] R/W 00000000 Lower 8 bits for duty cycle of internally generated PWM on ISINK(1)(2)(3)
(1) The default value in the register is 0x00. Any value written to the PWM_DUTY_1 and PWM_DUTY_2 registers is internally compared to PWM_DUTY_THR_L and PWM_DUTY_THR_H. A value below <PWM_DUTY_THR_H><PWM_DUTY_THR_L> is latched to the register but is internally ignored for setting the duty cycle and will result in a PWM signal with the minimum duty cycle defined by <PWM_DUTY_THR_H><PWM_DUTY_THR_L>
(2) A new value in PWM_DUTY_L and PWM_DUTY_H is internally valid after writing to PWM_DUTY_H AND the dithering cycle is completed, therefore PWM_DUTY_L should be written to first.
(3) A Duty Cycle of 1% or less may not be visible when the PWM frequency is 3KHz. At 24KHz, a Duty Cycle of 8% or less may not be visible.

7.6.13 PWM_DUTY_H Register Address: 0Ch

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Figure 27. PWM_DUTY_H Register
PWM_DUTY_H B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function PWM
_DC[9]; MSB
PWM
_DC[8]
Default 0 0 0 0 0 0 see Note1 see Note1
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R R R R R/W R/W
LEGEND: R/W = Read/Write; R = Read only;

Table 15. PWM_DUTY_H Register Field Descriptions

Bit Field Type Reset Description
Bit 7:2 R 000000
Bit 1:0 PWM_DC[9:8] R/W 00 Higher 2 Bits for duty cycle of internally generated PWM on ISINK(1)(2)(3)
PWM_DC[9:0] 00h = 0% duty cycle
3FFh = 99.9% duty cycle
(1) The default value in the register is 0x00. Any value written to the PWM_DUTY_L and PWM_DUTY_H registers is internally compared to PWM_DUTY_THR_L and PWM_DUTY_THR_H. A value below <PWM_DUTY_THR_H><PWM_DUTY_THR_L> is latched to the register but is internally ignored for setting the duty cycle and will result in a PWM signal with the minimum duty cycle defined by <PWM_DUTY_THR_H><PWM_DUTY_THR_L>
(2) A new value in PWM_DUTY_L and PWM_DUTY_H is internally valid after writing to PWM_DUTY_H AND the dithering cycle is completed, therefore PWM_DUTY_L should be written to first.
(3) A Duty Cycle of 1% or less may not be visible when the PWM frequency is 3KHz. At 24KHz, a Duty Cycle of 8% or less may not be visible.

7.6.14 RESERVED Register Address: 0Dh

Reserved

7.6.15 SPARE Register Address: 0Eh

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Figure 28. SPARE Register
SPARE B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function SPARE[7] SPARE[6] SPARE[5] SPARE[4] SPARE[3] SPARE[2] SPARE[1] SPARE[0]
Default 0 0 0 0 0 0 0 0
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only;

Table 16. SPARE Register Field Descriptions

Bit Field Type Reset Description
Bit 7:0 SPARE[7:0] R/W 00000000 Spare Register Bits

7.6.16 4K_OTP_PASSWORD Register Address: 0Fh

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Figure 29. 4K_OTP_PASSWORD Register
4K_OTP_PASSWORD B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function PW[7] PW[6] PW[5] PW[4] PW[3] PW[2] PW[1] PW[0]
Default 0 0 0 0 0 0 0 0
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write W W W W W W W W
LEGEND: R/W = Read/Write; R = Read only;

Table 17. 4K_OTP_PASSWORD Register Field Descriptions

Bit Field Type Reset Description
Bit 7:0 PW[7:0] W 00000000 User 4K OTP Password Register:
The correct password enables the qualifier for writing to the User 4K OTP.
The password is Implemented as a 2 Byte sequential write which must be performed back to back with no restriction on the delay between the writes.
If the correct password is not set, writing to the User 4K OTP memory is disabled.