JAJSLQ9C February   2016  – August 2021 TPS65981

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Requirements and Characteristics
    6. 7.6  Power Supervisor Characteristics
    7. 7.7  Power Consumption Characteristics
    8. 7.8  Cable Detection Characteristics
    9. 7.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 7.10 USB-PD TX Driver Voltage Adjustment Parameter
    11. 7.11 Port Power Switch Characteristics
    12. 7.12 Port Data Multiplexer Switching Characteristics
    13. 7.13 Port Data Multiplexer Clamp Characteristics
    14. 7.14 Port Data Multiplexer SBU Detection Requirements
    15. 7.15 Port Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics
    16. 7.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics
    17. 7.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics
    18. 7.18 Analog-to-Digital Converter (ADC) Characteristics
    19. 7.19 Input-Output (I/O) Requirements and Characteristics
    20. 7.20 I2C Slave Requirements and Characteristics
    21. 7.21 SPI Controller Characteristics
    22. 7.22 BUSPOWERZ Configuration Requirements
    23. 7.23 Single-Wire Debugger (SWD) Timing Requirements
    24. 7.24 Thermal Shutdown Characteristics
    25. 7.25 HPD Timing Requirements and Characteristics
    26. 7.26 Oscillator Requirements and Characteristics
    27. 7.27 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  USB-PD Physical Layer
        1. 9.3.1.1 USB-PD Encoding and Signaling
        2. 9.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.1.4 USB-PD BMC Transmitter
        5. 9.3.1.5 USB-PD BMC Receiver
      2. 9.3.2  Cable Plug and Orientation Detection
        1. 9.3.2.1 Configured as a DFP
        2. 9.3.2.2 Configured as a UFP
        3. 9.3.2.3 Dead-Battery or No-Battery Support
      3. 9.3.3  Port Power Switches
        1. 9.3.3.1  5-V Power Delivery
        2. 9.3.3.2  5V Power Switch as a Source
        3. 9.3.3.3  PP_5V0 Current Sense
        4. 9.3.3.4  PP_5V0 Current Limit
        5. 9.3.3.5  Internal HV Power Delivery
        6. 9.3.3.6  Internal HV Power Switch as a Source
        7. 9.3.3.7  Internal HV Power Switch as a Sink
        8. 9.3.3.8  Internal HV Power Switch Current Sense
        9. 9.3.3.9  Internal HV Power Switch Current Limit
        10. 9.3.3.10 External HV Power Delivery
        11. 9.3.3.11 External HV Power Switch as a Source with RSENSE
        12. 9.3.3.12 External HV Power Switch as a Sink With RSENSE
        13. 9.3.3.13 External HV Power Switch as a Sink Without RSENSE
        14. 9.3.3.14 External Current Sense
        15. 9.3.3.15 External Current Limit
        16. 9.3.3.16 Soft Start
        17. 9.3.3.17 BUSPOWERZ
        18. 9.3.3.18 Voltage Transitions on VBUS through Port Power Switches
        19. 9.3.3.19 HV Transition to PP_RV0 Pull-down on VBUS
        20. 9.3.3.20 VBUS Transition to VSAFE0V
        21. 9.3.3.21 C_CC1 and C_CC2 Power Configuration and Power Delivery
        22. 9.3.3.22 PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        23. 9.3.3.23 PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 9.3.4  USB Type-C® Port Data Multiplexer
        1. 9.3.4.1 USB Top and Bottom Ports
        2. 9.3.4.2 Multiplexer Connection Orientation
        3. 9.3.4.3 SBU Crossbar Multiplexer
        4. 9.3.4.4 Signal Monitoring and Pull-up and Pull-down
        5. 9.3.4.5 Port Multiplexer Clamp
        6. 9.3.4.6 USB2.0 Low-Speed Endpoint
        7. 9.3.4.7 Battery Charger (BC1.2) Detection Block
        8. 9.3.4.8 BC1.2 Data Contact Detect
        9. 9.3.4.9 BC1.2 Primary and Secondary Detection
      5. 9.3.5  Power Management
        1. 9.3.5.1 Power-On and Supervisory Functions
        2. 9.3.5.2 Supply Switch-Over
        3. 9.3.5.3 RESETZ and MRESET
      6. 9.3.6  Digital Core
      7. 9.3.7  USB-PD BMC Modem Interface
      8. 9.3.8  System Glue Logic
      9. 9.3.9  Power Reset Congrol Module (PRCM)
      10. 9.3.10 Interrupt Monitor
      11. 9.3.11 ADC Sense
      12. 9.3.12 I2C Slave
      13. 9.3.13 SPI Controller
      14. 9.3.14 Single-Wire Debugger Interface
      15. 9.3.15 DisplayPort HPD Timers
      16. 9.3.16 ADC
        1. 9.3.16.1 ADC Divider Ratios
        2. 9.3.16.2 ADC Operating Modes
        3. 9.3.16.3 Single Channel Readout
        4. 9.3.16.4 Round-Robin Automatic Readout
        5. 9.3.16.5 One Time Automatic Readout
      17. 9.3.17 I/O Buffers
        1. 9.3.17.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 9.3.17.2 IOBUF_OD
        3. 9.3.17.3 IOBUF_PORT
        4. 9.3.17.4 IOBUF_I2C
        5. 9.3.17.5 IOBUF_GPIOHSPI
        6. 9.3.17.6 IOBUF_GPIOHSSWD
      18. 9.3.18 Thermal Shutdown
      19. 9.3.19 Oscillators
    4. 9.4 Device Functional Modes
      1. 9.4.1 Boot Code
      2. 9.4.2 Initialization
      3. 9.4.3 I2C Configuration
      4. 9.4.4 Dead-Battery Condition
      5. 9.4.5 Application Code
      6. 9.4.6 Flash Memory Read
      7. 9.4.7 Invalid Flash Memory
    5. 9.5 Programming
      1. 9.5.1 SPI Controller Interface
      2. 9.5.2 I2C Slave Interface
        1. 9.5.2.1 I2C Interface Description
        2. 9.5.2.2 I2C Clock Stretching
        3. 9.5.2.3 I2C Address Setting
        4. 9.5.2.4 Unique Address Interface
        5. 9.5.2.5 I2C Pin Address Setting
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Fully-Featured USB Type-C® and PD Charger Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 External FET Path Components (PP_EXT and RSENSE)
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 TPS65981 External Flash
          2. 10.2.1.2.2 Debug Control (DEBUG_CTL) and I2C (I2C) Resistors
          3. 10.2.1.2.3 Oscillator (R_OSC) Resistor
          4. 10.2.1.2.4 VBUS Capacitor and Ferrite Bead
          5. 10.2.1.2.5 Soft Start (SS) Capacitor
          6. 10.2.1.2.6 USB Top (C_USB_T), USB Bottom (C_USB_B), and Sideband-Use (SBU) Connections
          7. 10.2.1.2.7 Port Power Switch (PP_EXT, PP_HV, PP_5V0, and PP_CABLE) Capacitors
          8. 10.2.1.2.8 Cable Connection (CCn) Capacitors and RPD_Gn Connections
          9. 10.2.1.2.9 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VIN_3V3, and VDDIO
        3. 10.2.1.3 Application Curve
      2. 10.2.2 USB Type-C® and PD Dock or Monitor Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Port Power Switch (PP_5V0 and PP_CABLE) Capacitors
          2. 10.2.2.2.2 HD3SS460 Control and DisplayPort Configuration
          3. 10.2.2.2.3 AC-DC Power Supply (Barrel Jack) Detection Circuitry
          4. 10.2.2.2.4 TPS65981 Control of Variable Buck Regulator Output Voltage (PP_HV)
          5. 10.2.2.2.5 TPS65981 and System Controller Interaction
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 3.3 V Power
      1. 11.1.1 VIN_3V3 Input Switch
      2. 11.1.2 VBUS 3.3-V LDO
    2. 11.2 1.8 V Core Power
      1. 11.2.1 1.8 V Digital LDO
      2. 11.2.2 1.8 V Analog LDO
    3. 11.3 VDDIO
      1. 11.3.1 Recommended Supply Load Capacitance
      2. 11.3.2 Schottky for Current Surge Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1  TPS65981 Recommended Footprint
      2. 12.1.2  Top TPS65981 Placement and Bottom Component Placement and Layout
      3. 12.1.3  Component Placement
      4. 12.1.4  Designs Rules and Guidance
      5. 12.1.5  Routing PP_HV, PP_EXT, PP_5V0, and VBUS
      6. 12.1.6  Routing Top and Bottom Passive Components
      7. 12.1.7  Thermal Pad Via Placement
      8. 12.1.8  Top Layer Routing
      9. 12.1.9  Inner Signal Layer Routing
      10. 12.1.10 Bottom Layer Routing
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RTQ|56
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-9928CD19-C7C8-4F68-9C44-F325212F67A4-low.gifFigure 6-1 RTQ Package 56-Pin VQFN With Exposed Thermal PadTop View
Table 6-1 Pin Functions
PIN CATEGORY I/O TYPE POR STATE DESCRIPTION
NAME NO.
AUX_N 55 Port Multiplexer Analog I/O Hi-Z System-side DisplayPort connection to the port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
AUX_P 54 Port Multiplexer Analog I/O Hi-Z System-side DisplayPort connection to the port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
BUSPOWERZ 22 Digital Core I/O and Control Analog Input Input (Hi-Z) General-purpose digital I/O 10. Sampled by ADC at boot. Tie pin to LDO_3V3 through a 100-kΩ resistor to disable PP_HV and PP_EXT power paths during dead-battery or no-battery boot conditions. Refer to the BUSPOWERZ table for more details.
C_CC1 13 Type-C Port Analog I/O Hi-Z Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC1 to GND.
C_CC2 15 Type-C Port Analog I/O Hi-Z Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC2 to GND.
C_SBU1 10 Type-C Port Analog I/O Hi-Z Port side-sideband use connection of port multiplexer.
C_SBU2 11 Type-C Port Analog I/O Hi-Z Port side-sideband use connection of port multiplexer.
C_USB_BN 9 Type-C Port Analog I/O Hi-Z Port-side bottom USB D– connection to the port multiplexer.
C_USB_BP 8 Type-C Port Analog I/O Hi-Z Port-side bottom USB D+ connection to the port multiplexer.
C_USB_TN 7 Type-C Port Analog I/O Hi-Z Port-side top USB D– connection to the port multiplexer.
C_USB_TP 6 Type-C Port Analog I/O Hi-Z Port-side top USB D+ connection to the port multiplexer.
DEBUG_CTL1 45 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 16. At power-up, pin state is sensed to determine bit 4 of the I2C address.
DEBUG_CTL2 44 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 17. At power-up, pin state is sensed to determine bit 5 of the I2C address.
DEBUG1 2 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 15. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO0 41 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 0. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO2 25 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 2. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO3 19 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 3. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO4 26 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 4. Configured as a hot-plug detect (HPD) transistor, HPD receiver, or both when DisplayPort mode is supported. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO5 23 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 5. Can be configured as a HPD receiver when DisplayPort mode is supported. Must be tied high or low through a 1-kΩ pull-up or pull-down resistor when used as a configuration input. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO6 20 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 6. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO7 38 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 7. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO8 1 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 8. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
HV_GATE1 31 External HV FET Control and Sense Analog Output Short to SENSEP External NFET gate control for high voltage power path. Float pin when unused.
HV_GATE2 32 External HV FET Control and Sense Analog Output Short to VBUS External NFET gate control for high voltage power path. Float pin when unused.
I2C_IRQZ 43 Digital Core I/O and Control Digital Output Hi-Z I2C port interrupt. Active low. Implement externally as an open-drain with a pull-up resistance. Float pin when unused.
I2C_SCL 47 Digital Core I/O and Control Digital I/O Digital Input I2C port serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistor when used or unused.
I2C_SDA 46 Digital Core I/O and Control Digital I/O Digital Input I2C port serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistor when used or unused.
LDO_1V8A 56 Low Current Power N/A Output of the 1.8-V LDO for core analog circuits. Bypass with capacitance CLDO_1V8A to GND.
LDO_1V8D 40 Low Current Power N/A Output of the 1.8-V LDO for core digital circuits. Bypass with capacitance CLDO_1V8D to GND.
LDO_3V3 51 Low Current Power N/A Output of the VBUS to 3.3-V LDO or connected to VIN_3V3 by a switch. Main internal supply rail. Used to power external flash memory. Bypass with capacitance CLDO_3V3 to GND.
LDO_BMC 48 Low Current Power N/A Output of the USB-PD BMC transceiver output level LDO. Bypass with capacitance CLDO_BMC to GND.
MRESET 24 Digital Core I/O and Control Digital I/O Hi-Z General-purpose digital I/O 11. Forces RESETZ to assert. By default, this pin asserts RESETZ when pulled high. The pin can be programmed to assert RESETZ when pulled low. Ground pin with a 1-MΩ resistor when unused in the application.
PP_5V0 27 High Current Power N/A 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused
28
PP_CABLE 14 High Current Power N/A 5-V supply for C_CC pins. Bypass with capacitance CPP_CABLE to GND when not tied to PP_5V0. Tie pin to PP_5V0 when unused.
PP_HV 33 High Current Power N/A HV supply for VBUS. Bypass with capacitance CPP_HV to GND. Tie pin to GND when unused
34
R_OSC 52 Digital Core I/O and Control Analog I/O Hi-Z External resistance setting for oscillator accuracy. Connect R_OSC to GND through resistance RR_OSC.
RESETZ 21 Digital Core I/O and Control Digital I/O Push-Pull Output (Low) General-purpose digital I/O 9. Active low reset output when VIN_3V3 is low (driven low on start-up). Float pin when unused.
RPD_G1 12 Type-C Port Analog I/O Hi-Z Tie pin to C_CC1 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise.
RPD_G2 16 Type-C Port Analog I/O Hi-Z Tie pin to C_CC2 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise.
SENSEN 29 External HV FET Control and Sense Analog Input Analog Input Positive sense for external high voltage power path current sense resistance. Short pin to VBUS when unused.
SENSEP 30 External HV FET Control and Sense Analog Input Analog Input Positive sense for external high voltage power path current sense resistance. Short pin to VBUS when unused.
SPI_CLK 37 Digital Core I/O and Control Digital Output Digital Input SPI serial clock. Connect pin directly to SPI Flash IC. Refer to the Boot Code section for more details on the SPI Flash.
SPI_POCI 35 Digital Core I/O and Control Digital Input Digital Input SPI serial controller input from peripheral. Tie pin to LDO_3V3 through a 3.3-kΩ resistor.
SPI_PICO 36 Digital Core I/O and Control Digital Output Digital Input SPI serial controller output to peripheral. Connect pin directly to SPI flash IC.
SPI_CSZ 39 Digital Core I/O and Control Digital Output Digital Input SPI chip select. Tie pin to LDO_3V3 through a 3.3-kΩ resistor.
SS 3 External HV FET Control and Sense Analog Output Driven Low Soft Start. Tie pin to capacitance CSS to ground.
SWD_CLK 50 Port Multiplexer Digital Input Resistive Pull High SWD serial clock. Float pin when unused.
SWD_DATA 49 Port Multiplexer Digital I/O Resistive Pull High SWD serial data. Float pin when unused.
USB_RP_N 5 Port Multiplexer Analog I/O Hi-Z System-side USB2.0 high-speed connection to the port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
USB_RP_P 4 Port Multiplexer Analog I/O Hi-Z System-side USB2.0 high-speed connection to the port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
VBUS 17 High Current Power N/A 5-V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass with capacitance CVBUS to GND.
18
VDDIO 42 Low Current Power N/A VDD for I/O. Some I/Os are reconfigurable to be powered from VDDIO instead of LDO_3V3. When VDDIO is not used, tie pin to LDO_3V3. When not tied to LDO_3V3 and used as a supply input, bypass with capacitance CVDDIO to GND.
VIN_3V3 53 Low Current Power N/A Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
GND (Thermal Pad) Ground Ground Hi-Z Ground. Connect directly to ground plane in accordance with the guidelines listed in the Layout Guidelines section to achieve the measured values in the Thermal Information table.