JAJSKZ8D April   2010  – December 2023 TPS74701-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics: IOUT = 50 mA
    7. 5.7 Typical Characteristics: VEN = VIN = 1.8 V, VOUT = 1.5 V
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Transient Response
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Output Noise
      4. 6.3.4 Enable and Shutdown
      5. 6.3.5 Power Good
      6. 6.3.6 Internal Current Limit
      7. 6.3.7 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input, Output, and Bias Capacitor Requirements
        2. 7.2.2.2 Programmable Soft-Start
        3. 7.2.2.3 Sequencing Requirements
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Layout Recommendations and Power Dissipation
        2. 7.4.1.2 Estimating Junction Temperature
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

at VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5.0 V, and TJ = –40°C to 125°C (Legacy Chip) and TJ = –40°C to 150°C (New Chip), (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF Internal reference (Adj.) TA = +25°C 0.796 0.8 0.804 V
VOUT Output voltage range VIN = 5 V, IOUT = 0.5 A VREF 3.6 V
Accuracy(1) 2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 0.5 A (Legacy Chip) –2 ±0.5 2 %
2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 0.5 A (New Chip)  –1.25 ±0.3 1.25
ΔVOUT(ΔVIN) Line regulation VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V (Legacy Chip) 0.03 %/V
VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V (New Chip)  0.001
ΔVOUT(ΔIOUT) Load regulation 50 mA ≤ IOUT ≤ 0.5 A (Legacy Chip)  0.09 %/A
50 mA ≤ IOUT ≤ 0.5 A (New Chip)  0.11
VDO VIN dropout voltage(2) IOUT = 0.5 A, VBIAS – VOUT(nom) ≥ 1.62 V (Legacy Chip)(3) 50 120 mV
IOUT = 0.5 A, VBIAS – VOUT(nom) ≥ 1.62 V (New Chip)(3) 20 40
VBIAS dropout voltage(2) IOUT = 0.5 A, VIN = VBIAS (Legacy Chip)  1.31 1.39 V
IOUT = 0.5 A, VIN = VBIAS (New Chip)  1.1 1.3
ICL Output current limit VOUT = 80% × VOUT(nom) (Legacy Chip) 800 1350 mA
VOUT = 80% × VOUT(nom) (New Chip)  800 1350
IBIAS BIAS pin current (Legacy Chip)  1 2 mA
(New Chip)  1 1.2
ISHDN Shutdown supply current (IGND) VEN ≤ 0.4 V (Legacy Chip) 1 50 µA
VEN ≤ 0.4 V (New Chip) 1 10
IFB Feedback pin current (Legacy Chip)  –1 0.15 1 µA
(New Chip)  –30 0.15 30 nA
PSRR Power-supply rejection (VIN to VOUT) 1 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) 60 dB
1 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (New Chip) 76
300 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) 30
300 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (New CHip)  50
Power-supply rejection (VBIAS to VOUT) 1 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) 50
1 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (New Chip) 59
300 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) 30
300 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (New Chip) 49
Vn Output noise voltage BW = 100 Hz to 100 kHz, IOUT = 0.5 A, CSS = 1 nF (Legacy Device) 25 × VOUT μVrms
BW = 100 Hz to 100 kHz, IOUT = 0.5 A, CSS = 1 nF (New Chip) 20 × VOUT
tSTR Minimum startup time RLOAD for IOUT = 0.5 A, CSS = open (Legacy Device) 200 µs
RLOAD for IOUT = 0.5 A, CSS = open (New Chip) 250
ISS Soft-start charging current VSS = 0.4 V (Legacy Chip) 440 nA
VSS = 0.4 V (New Chip) 530
VEN(hi) Enable input high level 1.1 5.5 V
VEN(lo) Enable input low level 0 0.4 V
VEN(hys) Enable pin hysteresis (Legacy Chip) 50 mV
(New Chip) 55
VEN(dg) Enable pin deglitch time 20 µs
IEN Enable pin current VEN = 5 V (Legacy Chip) 0.1 1 µA
VEN = 5 V (New Chip) 0.1 0.3
VIT PG trip threshold VOUT decreasing 85 90 94 %VOUT
VHYS PG trip hysteresis 3 %VOUT
VPG(lo) PG output low voltage IPG = 1 mA (sinking), VOUT < VIT (Legacy Chip) 0.3 V
IPG = 1 mA (sinking), VOUT < VIT (New Chip) 0.125
IPG(lkg) PG leakage current VPG = 5.25 V, VOUT > VIT (Legacy Chip) 0.1 1 µA
VPG = 5.25 V, VOUT > VIT (New Chip) 0.1 0.05
TSD Thermal shutdown temperature Shutdown, temperature increasing 165 ℃
Reset, temperature decreasing 140
(1) Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
(3) 1.62 V is a test condition of this device and can be adjusted by referring to Figure 5-29.