JAJS012J October   2004  – November 2018 TPS75003

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 Buck Converter
      2. 6.6.2 LDO Converter
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Operation (Buck Controllers)
      2. 7.3.2  Enable (Buck Controllers)
      3. 7.3.3  UVLO (Buck Controllers)
      4. 7.3.4  Current Limit (Buck Controllers)
      5. 7.3.5  Short-Circuit Protection (Buck Controllers)
      6. 7.3.6  Soft-Start (Buck Controllers)
      7. 7.3.7  LDO Operation
      8. 7.3.8  Internal Current Limit (LDO)
      9. 7.3.9  Enable Pin (LDO)
      10. 7.3.10 Dropout Voltage (LDO)
      11. 7.3.11 Transient Response (LDO)
      12. 7.3.12 Thermal Protection (LDO)
      13. 7.3.13 Power Dissipation (LDO)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Capacitor CIN1, CIN2 Selection (Buck Controllers)
        2. 8.2.2.2  Inductor Value Selection (Buck Controllers)
        3. 8.2.2.3  External PMOS Transistor Selection (Buck Controllers)
        4. 8.2.2.4  Diode Selection (Buck Controllers)
        5. 8.2.2.5  Output Capacitor Selection (Buck Controllers)
        6. 8.2.2.6  Output Voltage Ripple Effect on VOUT (Buck Controllers)
        7. 8.2.2.7  Soft-Start Capacitor Selection (Buck Controllers)
        8. 8.2.2.8  Output Voltage Setting Selection (Buck Controllers)
        9. 8.2.2.9  Input Capacitor Selection (LDO)
        10. 8.2.2.10 Output Capacitor Selection (LDO)
        11. 8.2.2.11 Soft-Start Capacitor Selection (LDO)
        12. 8.2.2.12 Setting Output Voltage (LDO)
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Considerations
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2V, VIN3 = 3.0V, VOUT3 = 2.5V, COUT1 = COUT2 = 47μF, COUT3 = 2.2μF, TA = –40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply and Logic
VINX Input Voltage Range
(IN1, IN2, IN3)(1) 		2.2 6.5 V
IQ Quiescent Current, IQ = IDGND + IAGND IOUT1 = IOUT2 = 0mA, IOUT3 = 1mA 75 150 μA
ISHDN Shutdown Supply Current VEN1 = VEN2 = VEN3 = 0V 0.05 3 μA
VIH1, 2 Enable High, enabled
(EN1, EN2)		 1.4 VINX V
VIH3 Enable High, enabled (EN3) 1.14 VIN3 V
VILX Enable Low, shutdown
(EN1, EN2, EN3)		 0 0.3 V
IENX Enable pin current
(EN1, EN2, EN3)		 0.01 0.5 μA
Buck Controllers 1 and 2
VOUT1,2 Adjustable Output Voltage Range(2) VFBX VINX V
VFB1,2 Feedback Voltage (FB1, FB2) 1.220 V
Feedback Voltage Accuracy(1)
(FB1, FB2)		 –2% 2%
IFB1,2 Current into FB1, FB2 pins 0.01 0.5 μA
VIS1,2 Reference Voltage for Current Sense 80 100 120 mV
IIS1,2 Current into IS1, IS2 Pins 0.01 0.5 μA
ΔVOUT%/ΔVIN Line Regulation(1) Measured with the circuit in Figure 18,
VOUT + 0.5V ≤ VIN ≤ 6.5V		 0.1 %/V
ΔVOUT%/ΔIOUT Load Regulation Measured with the circuit in Figure 18,
30mA ≤ I OUT ≤ 2A		 0.6 %/A
n1,2 Efficiency(3) Measured with the circuit in Figure 18, IOUT = 1A 94%
tSTR1,2 Startup Time(3) Measured with the circuit in Figure 18,
RL = 6Ω, COUT = 100μF, CSS = 2.2nF		 5 ms
RDS,ON1,2 Gate Driver P-Channel and N-Channel MOSFET On-Resistance VIN1,2 > 2.5V 4 Ω
VIN1,2 = 2.2V 6
ISW1,2 Gate Driver P-Channel and N-Channel MOSFET Drive Current 100 mA
tON Minimum On Time 1.36 1.55 1.84 μs
tOFF Minimum Off Time 0.44 0.65 0.86 μs
LDO
VOUT3 Output Voltage Range 1 6.5 – VDO V
VFB3 Feedback Pin Voltage 0.507 V
Feedback Pin Voltage Accuracy(1) 2.95V ≤ VIN3 ≤ 6.5V
1mA ≤ IOUT3 ≤ 300mA		 –4% 4%
ΔVOUT%/ΔVIN Line Regulation(1) VOUT3 + 0.5V ≤ VIN3 ≤ 6.5V 0.075 %/V
ΔVOUT%/ΔIOUT Load Regulation 10mA ≤ IOUT3 ≤ 300mA 0.01 %/mA
VDO Dropout Voltage
(VIN = VOUT(NOM) – 0.1)(4) 		IOUT3 = 300mA 250 350 mV
ICL3 Current Limit VOUT = 0.9 x VOUT(NOM) 375 600 1000 mA
IFB3 Current into FB3 pin 0.03 0.1 μA
Vn Output Noise BW = 100Hz – 100kHz,
IOUT3 = 300mA		 400 μVRMS
tSD Thermal Shutdown Temperature for LDO Shutdown, Temp Increasing 175 °C
Reset, Temp Decreasing 160
UVLO Under-Voltage Lockout Threshold VIN Rising 1.80 V
Under-Voltage Lockout Hysteresis VIN Falling 100 mV
(1) To be in regulation, minimum VIN1 (or VIN2) must be greater than VOUT1,NOM (or VOUT2,NOM) by an amount determined by external components. Minimum VIN3 = VOUT3 + VDO or 2.2V, whichever is greater.
(2) Maximum VOUT depends on external components and will be less than VIN.
(3) Depends on external components.
(4) VDO does not apply when VOUT + VDO < 2.2V.