SLVS822F March   2009  – April 2024 TPS798-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Dissipation Ratings
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Adjustable Operation
      2. 6.3.2 Output Capacitance and Transient Response
      3. 6.3.3 Calculating Junction Temperature
      4. 6.3.4 Protection Features
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low-Voltage Tracking
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Thermal Considerations
      2. 7.3.2 Thermal Layout Considerations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.4 Thermal Information

THERMAL METRIC(1)TPS798-Q1UNIT
DGN (HVSSOP)
8 PINS
RθJAJunction-to-ambient thermal resistance (JEDEC 51-5(2))57.1°C/W
Junction-to-ambient thermal resistance (JEDEC 51-7(3))130°C/W
RθJC(top)Junction-to-case (top) thermal resistance50.3°C/W
RθJBJunction-to-board thermal resistance30.6°C/W
ψJTJunction-to-top characterization parameter1.5°C/W
ψJBJunction-to-board characterization parameter30.3°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance6.5°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) The thermal data is based on using JEDEC 51-5. The copper pad is soldered to the thermal land pattern and using 5 by 8 thermal array (vias). Correct attachment procedure must be incorporated.
(3) The thermal data is based on using JEDEC 51-7. The copper pad is soldered to the thermal land. No thermal vias. Correct attachment procedure must be incorporated.