JAJSG67F September   2018  – March 2024 TPS7H2201-SEP , TPS7H2201-SP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: All Devices
    6. 6.6  Electrical Characteristics: CFP and KGD Options
    7. 6.7  Electrical Characteristics: HTSSOP Option
    8. 6.8  Switching Characteristics (All Devices)
    9. 6.9  Quality Conformance Inspection
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable, Undervoltage, and Overvoltage Protection
      2. 8.3.2 Adjustable Rise Time
      3. 8.3.3 Programmable Current Limiting
      4. 8.3.4 Programmable Fault Timer
      5. 8.3.5 Current Sense
      6. 8.3.6 Parallel Operation
      7. 8.3.7 Reverse Current Protection
      8. 8.3.8 Forward Leakage Current
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Redundancy
      2. 9.2.2 Protection
      3. 9.2.3 Design Requirements
      4. 9.2.4 Detailed Design Procedure
        1. 9.2.4.1 Undervoltage Lockout
        2. 9.2.4.2 Overvoltage Protection
        3. 9.2.4.3 Current Limit
        4. 9.2.4.4 Programmable Fault Timers
        5. 9.2.4.5 Soft Start Time
      5. 9.2.5 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DAP|32
  • KGD|0
  • HKR|16
サーマルパッド・メカニカル・データ
発注情報

9.4.1 Layout Guidelines

For best performance, all traces should be as short as possible. To be most effective, the input and output capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects. In general, the components should be placed close to the device such that traces remain as short as possible to avoid parasitic capacitance. In addition, due to the possibility of large power dissipation in fault conditions (short at VOUT), thermal vias should be placed in the PCB for the thermal pad.