JAJSOC5A march   2023  – april 2023 TPSF12C3

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Active EMI Filtering
        1. 8.3.1.1 Schematics
      2. 8.3.2 Capacitive Amplification
      3. 8.3.3 Integrated Line Rejection Filter
      4. 8.3.4 Compensation
      5. 8.3.5 Remote Enable
      6. 8.3.6 Supply Voltage UVLO Protection
      7. 8.3.7 Thermal Shutdown Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
  10. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – AEF Circuit for Grid Infrastructure Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Sense Capacitors
          2. 9.2.1.2.2 Inject Capacitor
          3. 9.2.1.2.3 Compensation Network
          4. 9.2.1.2.4 Injection Network
          5. 9.2.1.2.5 Surge Protection
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Design 1 – AEF Circuit for Grid Infrastructure Applications

Figure 9-3 shows a schematic diagram of a 10-kW high-density AC/DC regulator with conventional two-stage passive EMI filter. The CM chokes and Y-capacitors provide CM filtering, whereas the leakage inductance of the CM chokes and the X-capacitors provide DM filtering. Similar to TI reference designs TIDA-01606, the circuit uses a three-phase power-factor correction (PFC) stage with SiC power MOSFETs.

The PFC stage runs at a fixed switching frequency of 100 kHz. Even though the use of GaN or SiC power switches enables a high power density, the conventional passive EMI filter typically occupies over 20% of the total solution size.

GUID-20230316-SS0I-QWHD-JMFQ-JPJTRW17S3KX-low.svg Figure 9-1 Circuit Schematic of a Three-phase AC/DC Regulator With a Conventional Two-Stage Passive EMI Filter

The AC/DC stage increases the CM EMI signature based on the high dv/dt of the SiC power switches as well as the various switch-node parasitic capacitances to chassis ground.

This application example replaces the four Y-capacitors, designated as CY1, CY2, CY3 and CY4 in Figure 9-3, with a three-phase AEF circuit using the TPSF12C3. See Figure 9-3. The AEF circuit provides effective capacitive multiplication of the inject capacitor, which reduces the inductance values to maintain the target LC corner frequencies and thus the size, weight, and cost of the CM chokes, now designated as LCM1-AEF and LCM2-AEF. The total capacitance of the sense and inject capacitors is kept less than or equal to that of the replaced Y-capacitors, which results in the total line-frequency leakage current remaining effectively unchanged or reduced.

GUID-20230316-SS0I-VCVQ-ZRR8-3RXDZKKDLVJ3-low.svg Figure 9-2 Circuit Schematic of a Three-phase Regulator With AEF Circuit Connected