JAJSFG8D December   2005  – May 2018 TS321

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: TS321
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Gain Bandwidth Product
      3. 7.3.3 Slew Rate
      4. 7.3.4 Input Common-Mode Range
      5. 7.3.5 Stability With High Capacitive Loads
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.5 Stability With High Capacitive Loads

Operational amplifiers have reduced phase margin when there is a direct capacitance on the output. The stability is affected most when the amplifier is set to unity gain. Small signal response to a step input of 100 mV reveals the loop stability with a range of capacitors. See SLVA381 to correlate response waveform to phase margin. The responses at 1 nF or less indicate acceptable phase margin. The responses at 1 uF and above indicate good phase margin.

TS321 TS321CAPS.gifFigure 7. Small-Signal Response