JAJSCO5C November   2016  – June 2018 TUSB422

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      USB Type-Cスマートフォン
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 Cables, Adapters, and Direct Connect Devices
        1. 7.2.1.1 USB Type-C receptacles and Plugs
        2. 7.2.1.2 USB Type-C Cables
        3. 7.2.1.3 Direct Connect Devices
    3. 7.3 Feature Description
      1. 7.3.1  USB PD I2C Type-C Port Controller Interface (TCPC)
      2. 7.3.2  USB PD BMC PHY
      3. 7.3.3  DFP (Downstream Facing Port)
      4. 7.3.4  UFP (Upstream Facing Port)
      5. 7.3.5  DRP (Dual-Role Port)
      6. 7.3.6  Type-C Current Mode Advertising
      7. 7.3.7  VBUS Source Enable/Disable Control
      8. 7.3.8  VBUS Sink Enable/Disable Control
      9. 7.3.9  VBUS Monitoring
      10. 7.3.10 VBUS Discharge
      11. 7.3.11 VBUS to CC Short Detection from Legacy Charger
      12. 7.3.12 VBUS Power Source Requirements
      13. 7.3.13 VBUS Power Sink Requirements.
      14. 7.3.14 VCONN
      15. 7.3.15 Interrupts
      16. 7.3.16 Fast Role Swap
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unattached Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Power Role Swap
      4. 7.4.4 Debug Accessory
      5. 7.4.5 Dead Battery Mode
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1  CSR Registers
      2. 7.6.2  Vendor ID Byte 0 Register (address = 0x00) [reset = 0x51]
        1. Table 7. Vendor ID Byte 0 Register Field Descriptions
      3. 7.6.3  Vendor ID Byte 1 Register (address = 0x01) [reset = 0x04]
        1. Table 8. Vendor ID Byte 1 Register Field Descriptions
      4. 7.6.4  Product ID Byte 0 Register (address = 0x02) [reset = 0x22]
        1. Table 9. Product ID Byte 0 Register Field Descriptions
      5. 7.6.5  Product ID Byte 1 Register (address = 0x03) [reset = 0x04]
        1. Table 10. Product ID Byte 1 Register Field Descriptions
      6. 7.6.6  Device ID Byte 0 Register (address = 0x04) [reset = 0x00]
        1. Table 11. Device ID Byte 0 Register Field Descriptions
      7. 7.6.7  Device ID Byte 1 Register (address = 0x05) [reset = 0x01]
        1. Table 12. Device ID Byte 1 Register Field Descriptions
      8. 7.6.8  USB Type-C Revision Byte 0 Register (address = 0x06) [reset = 0x11]
        1. Table 13. USB Type-C Revision Byte 0 Register Field Descriptions
      9. 7.6.9  USB Type-C Revision Byte 1 Register (address = 0x07) [reset = 0x00]
        1. Table 14. USB Type-C Revision Byte 1 Descriptions
      10. 7.6.10 USB PD Revision Version Byte 0 Register (address = 0x08) [reset = 0x11]
        1. Table 15. USB PD Revision Version Byte 0 Descriptions
      11. 7.6.11 USB PD Revision Version Byte 1 Register (address = 0x09) [reset = 0x20]
        1. Table 16. USB PD Revision Version Byte 1 Descriptions
      12. 7.6.12 PD Interface Revision Byte 0 Register (address = 0x0A) [reset = 0x10]
        1. Table 17. PD Interface Revision Byte 0 Descriptions
      13. 7.6.13 PD Interface Revision Byte 1 Register (address = 0x0B) [reset = 0x10]
        1. Table 18. PD Interface Revision Byte 1 Descriptions
      14. 7.6.14 Alert Byte 0 Register (address = 0x10) [reset = 0x00]
        1. Table 19. Alert Byte 0 Register Descriptions
      15. 7.6.15 Alert Byte 1 Register (address = 0x11) [reset = 0x00]
        1. Table 20. Alert Byte 1 Register Descriptions
      16. 7.6.16 Alert Mask Byte 0 Register (address = 0x12) [reset = 0xFFh]
        1. Table 21. Alert Mask Byte 0 Register Descriptions
      17. 7.6.17 Alert Mask Byte 1 Register (address = 0x13) [reset = 0x0F]
        1. Table 22. Alert Mask Byte 1 Register Descriptions
      18. 7.6.18 Power Status Mask Register (address = 0x14) [reset = 0xFF]
        1. Table 23. Power Status Mask Register Descriptions
      19. 7.6.19 FAULT Status Mask Register (address = 0x15) [reset = 0x7F]
        1. Table 24. FAULT Status Mask Register Descriptions
      20. 7.6.20 Config Standard Output Register (address = 0x18) [reset = 0x60]
        1. Table 25. Config Standard Output Descriptions
      21. 7.6.21 TCPC Control Register (address = 0x19) [reset = 0x00]
        1. Table 26. TCPC Control Register Descriptions
      22. 7.6.22 ROLE Control Register (address = 0x1A) [reset = 0x0A]
        1. Table 27. ROLE Control Register Descriptions
      23. 7.6.23 FAULT Control Register (address = 0x1B) [reset = 0x06]
        1. Table 28. FAULT Control Register Descriptions
      24. 7.6.24 Power Control Register (address = 0x1C) [reset = 0x60]
        1. Table 29. Power Control Register Descriptions
      25. 7.6.25 CC Status Register (address = 0x1D) [reset = 0x00]
        1. Table 30. CC Status Register Descriptions
      26. 7.6.26 Power Status Register (address = 0x1E) [reset = 0x00]
        1. Table 31. Power Status Register Descriptions
      27. 7.6.27 Fault Status Register (address = 0x1F) [reset = 0x00]
        1. Table 32. Fault Status Register Descriptions
      28. 7.6.28 Command Register (address = 0x23) [reset = 0x00]
        1. Table 33. Command Register Descriptions
      29. 7.6.29 Device Capabilities 1 Byte 0 Register (address = 0x24) [reset = 0x98]
        1. Table 34. Device Capabilities 1 Byte 0 Descriptions
      30. 7.6.30 Device Capabilities 1 Byte 1 Register (address = 0x25) [reset = 0x1E]
        1. Table 35. Device Capabilities 1 Byte 1 Descriptions
      31. 7.6.31 Device Capabilities 2 Byte 0 Register (address = 0x26) [reset = 0xC5]
        1. Table 36. Device Capabilities 2 Byte 0 Register Descriptions
      32. 7.6.32 Device Capabilities 2 Byte 1 Register (address = 0x27) [reset = 0x00]
        1. Table 37. Device Capabilities 2 Byte 1 Register Descriptions
      33. 7.6.33 Standard Input Capabilities Register (address = 0x28) [reset = 0x00]
        1. Table 38. Standard Input Capabilities Register Descriptions
      34. 7.6.34 Standard Output Capabilities Register (address = 0x29) [reset = 0x00]
        1. Table 39. Standard Output Capabilities Register Descriptions
      35. 7.6.35 Message Header Info Register (address = 0x2E) [reset = 0x02]
        1. Table 40. Message Header Info Register Descriptions
      36. 7.6.36 Receiver Detect Register (address = 0x2F) [reset = 0x00]
        1. Table 41. Receiver Detect Register Descriptions
      37. 7.6.37 Receive Byte Count Register (address = 0x30) [reset = 0x00]
        1. Table 42. Receive Byte Count Register Descriptions
      38. 7.6.38 Receive Buffer Frame Type Register (address = 0x31) [reset = 0x00]
        1. Table 43. Receive Buffer Frame Type Register Descriptions
      39. 7.6.39 Receive Buffer Header Byte 0 Register (address = 0x32) [reset = 0x00]
        1. Table 44. Receive Buffer Header Byte 0 Descriptions
      40. 7.6.40 Receive Buffer Header Byte 1 Register (address = 0x33) [reset = 0x00]
        1. Table 45. Receive Buffer Header Byte 1 Descriptions
      41. 7.6.41 Receive Buffer Data Object 1 Through 7 Register (address = 0x34 through 0x4F) [reset = 0x00]
        1. Table 46. Receive Buffer Data Object 1 Through 7 Descriptions
      42. 7.6.42 Transmit Register (address = 0x50) [reset = 0x00]
        1. Table 47. Transmit Register Descriptions
      43. 7.6.43 Transmit Byte Count Register (address = 0x51) [reset = 0x00]
        1. Table 48. Transmit Byte Count Register Descriptions
      44. 7.6.44 Transmit Buffer Header Byte 0 Register (address = 0x52) [reset = 0x00]
        1. Table 49. Transmit Buffer Header Byte 0 Register Descriptions
      45. 7.6.45 Transmit Buffer Header Byte 1 Register (address = 0x53) [reset = 0x00]
        1. Table 50. Transmit Buffer Header Byte 1 Register Descriptions
      46. 7.6.46 Transmit Buffer Data Object 1 Through 7 Register (address = 0x54 through 0x6F) [reset = 0x00]
        1. Table 51. Transmit Buffer Data Object 1 Through 7 Register Descriptions
      47. 7.6.47 VBUS Voltage Byte 0 Register (address = 0x70) [reset = 0x00]
        1. Table 52. VBUS Voltage Byte 0 Descriptions
      48. 7.6.48 VBUS Voltage Byte 1 Register (address = 0x71) [reset = 0x00]
        1. Table 53. VBUS Voltage Byte 1 Register Descriptions
      49. 7.6.49 VBUS Sink Disconnect Threshold Byte 0 Register (address = 0x72) [reset = 0x00]
        1. Table 54. VBUS Sink Disconnect Threshold Byte 0 Register Descriptions
      50. 7.6.50 VBUS Sink Disconnect Threshold Byte 1 Register (address = 0x73) [reset = 0x00]
        1. Table 55. VBUS Sink Disconnect Threshold Byte 1 Register Descriptions
      51. 7.6.51 VBUS Stop Discharge Threshold Byte 0 Register (address = 0x74) [reset = 0x00]
        1. Table 56. VBUS Stop Discharge Threshold Byte 0 Register Descriptions
      52. 7.6.52 VBUS Stop Discharge Threshold Byte 1 Register (address = 0x75) [reset = 0x00]
        1. Table 57. VBUS Stop Discharge Threshold Byte 1 Register Descriptions
      53. 7.6.53 VBUS Voltage Alarm High Config Byte 0 Register (address = 0x76) [reset = 0x00]
        1. Table 58. VBUS Voltage Alarm High Config Byte 0 Register Descriptions
      54. 7.6.54 VBUS Voltage Alarm High Config Byte 1 Register (address = 0x77) [reset = 0x00]
        1. Table 59. VBUS Voltage Alarm High Config Byte 1 Register Descriptions
      55. 7.6.55 VBUS Voltage Alarm Low Config Byte 0 Register (address = 0x78) [reset = 0x00]
        1. Table 60. VBUS Voltage Alarm Low Config Byte 0 Register Descriptions
      56. 7.6.56 VBUS Voltage Alarm Low Config Byte 1 Register (address = 0x79) [reset = 0x00]
        1. Table 61. VBUS Voltage Alarm Low Config Byte 1 Register Descriptions
      57. 7.6.57 Vendor Interrupts Status Register (address = 0x90) [reset = 0x00]
        1. Table 62. Vendor Interrupts Status Register Descriptions
      58. 7.6.58 Vendor Interrupts Mask Register (address = 0x92) [reset = 0x00]
        1. Table 63. Vendor Interrupts Mask Register Descriptions
      59. 7.6.59 CC General Control Register (address = 0x94) [reset = 0x04]
        1. Table 64. CC General Control Register Descriptions
      60. 7.6.60 PHY BMC TX Control Register (address = 0x95) [reset = 0x00]
        1. Table 65. PHY BMC TX Control Register Descriptions
      61. 7.6.61 PHY BMC RX Control Register (address = 0x96) [reset = 0x00]
        1. Table 66. PHY BMC RX Control Register Descriptions
      62. 7.6.62 PHY BMC RX Status Register (address = 0x97) [reset = 0x00]
        1. Table 67. PHY BMC RX Status Register Descriptions
      63. 7.6.63 VBUS and VCONN Control Register (address = 0x98) [reset = 0x00]
        1. Table 68. VBUS and VCONN Control Descriptions
      64. 7.6.64 OTSD Control Register (address = 0x99) [reset = 0x00]
        1. Table 69. OTSD Control Register Descriptions
      65. 7.6.65 LFO Timer Low Register (address = 0xA0) [reset = 0x00]
        1. Table 70. LFO Timer Low Register Descriptions
      66. 7.6.66 LFO Timer High Register (address = 0xA1) [reset = 0x00]
        1. Table 71. LFO Timer High Register Descriptions
      67. 7.6.67 Page Select Register (address = 0xFF) [reset = 0x00]
        1. Table 72. Page Select Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • YFP|9
サーマルパッド・メカニカル・データ
発注情報

7.6.21 TCPC Control Register (address = 0x19) [reset = 0x00]

Figure 29. TCPC Control Register
7 6 5 4 3 2 1 0
Reserved DEBUG_ACC_CTL I2C_CLOCK_STRETCHING_CTL BIST_TEST_MODE PLUG_ORIENTATION
R R/W R R R/W R/W
LEGEND: R/W = Read/Write; R = Read only

Table 26. TCPC Control Register Descriptions

Bit Field Type Reset Description
7:5 Reserved R 000 Reserved
4 DEBUG_ACC_CTL R/W 0 0b: Controlled by TUSB422 (power on default)
1b: Controlled by TCPM. The TCPM writes 1b to this register to take over control of asserting the DebugAccessoryConnected#.
This field has no meaning for TUSB422.
3:2 I2C_CLOCK_STRETCHING_CTL R 00 Clock Stretching Control
00b: Disable clock stretching. TUSB422 will not perform any clock stretching during I2C transfers.
01b: Reserved
10b: Enable clock stretching. TUSB422 is allowed limited clock stretching during each I2C Transfer.
11b: Enable clock stretching only if the Alert pin is not asserted. As soon as Alert is asserted, clock stretching is disabled by the TUSB422.
TUSB422 does not support clock stretching
1 BIST_TEST_MODE R/W 0 Setting this bit to 1 is intended to be used only when a USB compliance tester is using USB BIST Test Data to test the PHY layer of the TUSB422. The TCPM should clear this bit when a detach is detected.
0: Normal Operation. Incoming messages enabled by RECEIVE_DETECT passed to TCPM via Alert.
1: BIST Test Mode. Incoming messages enabled by RECEIVE_DETECT result in GoodCRC response but will not be passed to the TCPM via Alert.
0 PLUG_ORIENTATION R/W 0 0b: When VCONN is enabled, apply it to the CC2 pin. Monitor the CC1 pin for BMC communications if PD messaging is enabled.
1b: When VCONN is enabled, apply it to the CC1 pin. Monitor the CC2 pin for BMC communications if PD messaging is enabled.