JAJSOK5Q
March 2011 – March 2024
TUSB7320
,
TUSB7340
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
3.3-V I/O Electrical Characteristics
5.6
Input Clock Specification
5.7
Input Clock 1.8-V DC Characteristics
5.8
Crystal Specification
5.9
TUSB7320 Power Consumption
5.10
TUSB7340 Power Consumption
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
PHY Control
6.3.1.1
Output Voltage Swing Control
6.3.1.1.1
De-Emphasis Control
6.3.1.2
Adaptive Equalizer
6.3.2
Input Clock
6.3.2.1
Clock Source Requirements
6.3.2.2
External Clock
6.3.2.3
External Crystal
6.4
Programming
6.4.1
Two-Wire Serial-Bus Interface
6.4.1.1
Serial-Bus Interface Implementation
6.4.1.2
Serial-Bus Interface Protocol
6.4.1.3
Serial-Bus EEPROM Application
6.4.2
System Management Interrupt
7
Application and Implementation
7.1
Application Information
7.1.1
特長
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Upstream Implementation
7.2.2.2
Downstream Ports Implementation
7.2.2.3
PCI Express Connector
7.2.2.4
1.1-V Regulator
7.2.2.5
5-V VBUS Options
7.2.3
Application Curves
7.3
Power Supply Recommendations
7.3.1
Power-Up and Power-Down Sequencing
7.3.1.1
Power-Up Sequence
7.3.1.2
Power-Down Sequence
7.3.2
PCI Express Power Management
7.4
Layout
7.4.1
Layout Guidelines
7.4.1.1
High-Speed Differential Routing
7.4.1.2
SuperSpeed Differential Routing
7.4.2
Layout Example
8
Register Maps
8.1
Classic PCI Configuration Space
8.1.1
The PCI Configuration Map
8.1.2
Vendor ID Register
8.1.3
Device ID Register
8.1.4
Command Register
8.1.5
Status Register
8.1.6
Class Code and Revision ID Register
8.1.7
Cache Line Size Register
8.1.8
Latency Timer Register
8.1.9
Header Type Register
8.1.10
BIST Register
8.1.11
Base Address Register 0
8.1.12
Base Address Register 1
8.1.13
Base Address Register 2
8.1.14
Base Address Register 3
8.1.15
Subsystem Vendor ID Register
8.1.16
Subsystem ID Register
8.1.17
Capabilities Pointer Register
8.1.18
Interrupt Line Register
8.1.19
Interrupt Pin Register
8.1.20
Min Grant Register
8.1.21
Max Latency Register
8.1.22
Capability ID Register
8.1.23
Next Item Pointer Register
8.1.24
Power Management Capabilities Register
8.1.25
Power Management Control/Status Register
8.1.26
Power Management Bridge Support Extension Register
8.1.27
Power Management Data Register
8.1.28
MSI Capability ID Register
8.1.29
Next Item Pointer Register
8.1.30
MSI Message Control Register
8.1.31
MSI Lower Message Address Register
8.1.32
MSI Upper Message Address Register
8.1.33
MSI Message Data Register
8.1.34
Serial Bus Release Number Register (SBRN)
8.1.35
Frame Length Adjustment Register (FLADJ)
8.1.36
PCI Express Capability ID Register
8.1.37
Next Item Pointer Register
8.1.38
PCI Express Capabilities Register
8.1.39
Device Capabilities Register
8.1.40
Device Control Register
8.1.41
Device Status Register
8.1.42
Link Capabilities Register
8.1.43
Link Control Register
8.1.44
Link Status Register
8.1.45
Device Capabilities 2 Register
8.1.46
Device Control 2 Register
8.1.47
Link Control 2 Register
8.1.48
Link Status 2 Register
8.1.49
Serial Bus Data Register
8.1.50
Serial Bus Index Register
8.1.51
Serial Bus Target Address Register
8.1.52
Serial Bus Control and Status Register
8.1.53
GPIO Control Register
8.1.54
GPIO Data Register
8.1.55
MSI-X Capability ID Register
8.1.56
Next Item Pointer Register
8.1.57
MSI-X Message Control Register
8.1.58
MSI-X Table Offset and BIR Register
8.1.59
MSI-X PBA Offset and BIR Register
8.1.60
Subsystem Access Register
8.1.61
General Control 0 Register
8.1.62
General Control 1 Register
8.1.63
General Control 2 Register
8.1.64
USB Control Register
8.1.65
De-Emphasis and Swing Control Register
8.1.66
Equalizer Control Register
8.1.67
Custom PHY Transmit/Receive Control Register
8.2
PCI Express Extended Configuration Space
8.2.1
The PCI Express Extended Configuration Map
8.2.2
Advanced Error Reporting Capability Register
8.2.3
Next Capability Offset / Capability Version Register
8.2.4
Uncorrectable Error Status Register
8.2.5
Uncorrectable Error Mask Register
8.2.6
Uncorrectable Error Severity Register
8.2.7
Correctable Error Severity Register
8.2.8
Correctable Error Mask Register
8.2.9
Advanced Error Capabilities and Control Register
8.2.10
Header Log Register
8.2.11
Device Serial Number Capability ID Register
8.2.12
Next Capability Offset/Capability Version Register
8.2.13
Device Serial Number Register
8.3
xHCI Memory Mapped Register Space
8.3.1
The xHCI Register Map
8.3.2
Host Controller Capability Registers
8.3.2.1
Capability Registers Length
8.3.2.2
Host Controller Interface Version Number
8.3.2.3
Host Controller Structural Parameters 1
8.3.2.4
Host Controller Structural Parameters 2
8.3.2.5
Host Controller Structural Parameters 3
8.3.2.6
Host Controller Capability Parameters
8.3.2.7
Doorbell Offset
8.3.2.8
Runtime Register Space Offset
8.3.3
Host Controller Operational Registers
8.3.3.1
USB Command Register
8.3.3.2
USB Command Register
8.3.3.3
USB Status Register
8.3.3.4
Page Size Register
8.3.3.5
Device Notification Control Register
8.3.3.6
Command Ring Control Register
8.3.3.7
Device Context Base Address Array Pointer Register
8.3.3.8
Configure Register
8.3.3.9
Port Status and Control Register
8.3.3.10
Port PM Status and Control Register (USB 3.0 Ports)
8.3.3.11
Port PM Status and Control Register (USB 2.0 Ports)
8.3.3.12
Port Link Info Register
8.3.4
Host Controller Runtime Registers
8.3.4.1
Microframe Index Register
8.3.4.2
Interrupter Management Register
8.3.4.3
Interrupter Moderation Register
8.3.4.4
Event Ring Segment Table Size Register
8.3.4.5
Event Ring Segment Table Base Address Register
8.3.4.6
Event Ring Dequeue Pointer Register
8.3.5
Host Controller Doorbell Registers
8.3.6
xHCI Extended Capabilities Registers
8.3.6.1
USB Legacy Support Capability Register
8.3.6.2
USB Legacy Support Control/Status Register
8.3.6.3
xHCI Supported Protocol Capability Register (USB 2.0)
8.3.6.4
xHCI Supported Protocol Name String Register (USB 2.0)
8.3.6.5
xHCI Supported Protocol Port Register (USB 2.0)
8.3.6.6
xHCI Supported Protocol Capability Register (USB 3.0)
8.3.6.7
xHCI Supported Protocol Name String Register (USB 3.0)
8.3.6.8
xHCI Supported Protocol Port Register (USB 3.0)
8.4
MSI-X Memory Mapped Register Space
8.4.1
The MSI-X Table and PBA in Memory Mapped Register Space
8.5
The MSI-X Table and PBA in Memory Mapped Register Space
9
Device and Documentation Support
9.1
Device Support
9.1.1
サード・パーティ製品に関する免責事項
9.1.2
Device Nomenclature
9.2
Documentation Support
9.2.1
Related Documentation
9.3
ドキュメントの更新通知を受け取る方法
9.4
サポート・リソース
9.5
Trademarks
9.6
静電気放電に関する注意事項
9.7
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RKM|100
MPQF258B
サーマルパッド・メカニカル・データ
RKM|100
QFND273C
発注情報
jajsok5q_oa
jajsok5q_pm
2
アプリケーション
ラック・サーバー、
マイクロサーバー、タワー・サーバー
高性能コンピューティング
ストレージ・エリア・ネットワーク (SAN) とホスト・バス・アダプタ (HBA) カード
デスクトップ PC またはマザーボード