JAJSHB3G September 2011 – May 2019 TXB0304
PRODUCTION DATA.
The TXB0304 and TXBN0304 architecture (see Figure 4) does not require a direction-control signal to control the direction of data flow from A to B or from B to A. In a dc state, the output drivers of the TXB0304 can maintain a high or low, but are designed to be weak, so that they can be overdriven by an external driver when data on the bus starts flowing the opposite direction. The output one shots detect rising or falling edges on the A or B ports. During a rising edge, the one shot turns on the PMOS transistors (T1, T3) for a short duration, which speeds up the low-to-high transition. Similarly, during a falling edge, the one shot turns on the NMOS transistors (T2, T4) for a short duration, which speeds up the high-to-low transition. The typical output impedance during output transition is 30 Ω at VCCO = 0.9 V to 1 V, 10 Ω at VCCO = 1.1 V to 1.7 V, and 5 Ω at VCCO = 1.8 V to 3.3 V.