JAJSQ34A april   2023  – august 2023 UCC14131-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Insulation Specifications
    6. 7.6 Electrical Characteristics
    7. 7.7 Safety Limiting Values
  9. 8 Safety-Related Certifications
  10. 9 Insulation Characteristics
  11. 10Typical Characteristics
  12. 11Detailed Description
    1. 11.1 Overview
    2. 11.2 Functional Block Diagram
    3. 11.3 Feature Description
      1. 11.3.1 Power Stage Operation
        1. 11.3.1.1 VDD-VEE Voltage Regulation
        2. 11.3.1.2 COM-VEE Voltage Regulation
        3. 11.3.1.3 Power Handling Capability
      2. 11.3.2 Output Voltage Soft Start
      3. 11.3.3 ENA and PG
      4. 11.3.4 Protection Functions
        1. 11.3.4.1 Input Undervoltage Lockout
        2. 11.3.4.2 Input Overvoltage Lockout
        3. 11.3.4.3 Output Undervoltage Protection
        4. 11.3.4.4 Output Overvoltage Protection
        5. 11.3.4.5 Overpower Protection
        6. 11.3.4.6 Overtemperature Protection
    4. 11.4 Device Functional Modes
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1 Capacitor Selection
        2. 12.2.2.2 Single RLIM Resistor Selection
        3. 12.2.2.3 RDR Circuit Component Selection
        4. 12.2.2.4 Feedback Resistors Selection
    3. 12.3 System Examples
    4. 12.4 Power Supply Recommendations
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information
  16. 15Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.3.2 Output Voltage Soft Start

UCC14131-Q1 power-up diagram of two output rails with soft start is shown in Figure 11-5. After VVIN > VVIN_UVLOP and ENA is pulled high, the soft-start sequence starts with burst duty cycle control with soft duty cycle increment. The burst duty cycle gradually increases from 12.5% to 50% over time by the primary-side control signal (DSS_PRI), so both VVDD-VEE and VCOM-VEE increase ratiometrically with a controlled shallow rising slope. When VVDD-VEE is increased above VVDD_UVLOS, there is a sufficient bias voltage for the feedback-loop communication channel, so the burst feedback control on the secondary side takes over. As a result, the DSS_PRI is pulled high and does not affect burst duty cycle anymore. The burst duty cycle is determined by comparing VFBVDD and VREF. VREF increases from 0.9V to 2.5 V with seven increment steps, where the first 1-V step boosts VREF from 0.9V to 1.9V, and then the following six 0.1-V steps boosts VREF from 1.9V to 2.5V. Each step lasts 128 µs. After VVDD-VEE > VVDD_UVP, the RLIM source-sink regulator for VCOM-VEE is enabled. The polarity of source or sink current of RLIM pin is determined by comparing VFBVEE and VREF so as to keep VCOM-VEE in tight regulation. Once VVDD-VEE or VCOM-VEE rises across its UVP threshold, there is a 3-ms (typical) deglitch time for VVDD-VEE UVP and VCOM-VEE UVP and OVP, and then the power good signal is issued by pulling PG voltage low. The 3-ms (typical) deglitch time is only applied during start up before the power good signal is issued. It provides enough time for both VVDD-VEE and VCOM-VEE to settle in their hysteresis band of regulation after start up, so that the converter does not shut down due to the overshoot or undershoot during start up.

The soft-start feature greatly reduces the input inrush current during power-up. In addition, if VVDD-VEE cannot reach to VVDD_UVLOS within tSOFT_START_TIME_OUT, then the device shuts down in a safe-state. The soft-start time-out protects the module under output short circuit condition or over-load during power up.

GUID-2E65F43C-4B85-4E22-901E-3CD35BEB0F04-low.svgFigure 11-5 Output voltage Soft-Start Diagram