JAJSR37A August   2023  – September 2023 UCC14340-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Insulation Specifications
    6. 7.6 Safety-Related Certifications
    7. 7.7 Electrical Characteristics
    8. 7.8 Safety Limiting Values
    9. 7.9 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 機能ブロック図
    3. 8.3 Feature Description
      1. 8.3.1 Power Stage Operation
        1. 8.3.1.1 VDD-VEE Voltage Regulation
        2. 8.3.1.2 COM-VEE Voltage Regulation
        3. 8.3.1.3 Power Handling Capability
      2. 8.3.2 Output Voltage Soft Start
      3. 8.3.3 ENA and PG
      4. 8.3.4 Protection Functions
        1. 8.3.4.1 Input Undervoltage Lockout
        2. 8.3.4.2 Input Overvoltage Lockout
        3. 8.3.4.3 Output Undervoltage Protection
        4. 8.3.4.4 Output Overvoltage Protection
        5. 8.3.4.5 Overpower Protection
        6. 8.3.4.6 Overtemperature Protection
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Capacitor Selection
        2. 9.2.2.2 Single RLIM Resistor Selection
        3. 9.2.2.3 RDR Circuit Component Selection
        4. 9.2.2.4 Feedback Resistors Selection
  11. 10System Examples
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information
  16. 15Tape and Reel Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Overview

UCC14340-Q1 device is suitable for applications that have limited board space and require more integration. These devices are also suitable for very-high voltage applications, where power transformers meeting the required isolation specifications are bulky and expensive. The low-profile, low-center of gravity, and low weight provides a higher vibration tolerance than systems using large bulky transformers. The device is easy-to-use and provides flexibility to adjust both positive and negative output voltages as needed when optimizing the gate voltage for maximum efficiency while protecting gate oxide from over-stress with its tight voltage regulation accuracy.

The device integrates a high-efficiency, low-emissions isolated DC/DC converter for powering the gate drive of SiC or IGBT power devices in traction inverter motor drives, industrial motor drives, or other high voltage DC/DC converters. This DC/DC converter provides greater than 1.5 W of power for 13.5 V < VVIN < 16.5 V for regulated rails.

The integrated DC/DC converter uses switched mode operation and proprietary circuit techniques to reduce power losses and boost efficiency. Specialized control mechanisms, clocking schemes, and the use of an on- chip transformer provide high efficiency and low radiated emissions.

The integrated transformer provides power delivery throughout a wide temperature range while maintaining a 3000-VRMS isolation, and an 850-VRMS continuous working voltage. The low isolation capacitance of the transformer provides high CMTI allowing fast dv/dt switching and higher switching frequencies, while emitting less noise.

The VVIN supply is provided to the primary-side power controller that switches the input stage connected to the integrated transformer. Power is transferred to the secondary-side output stage, and regulated to a level set by the resistor divider connected between the (VDD – VEE) pin and the FBVDD pin with respect to the VEE pin. The output voltage is adjustable with an external resistor divider allowing a wide (VDD – VEE) range.

For optimal performance ensure to maintain the VVIN input voltage within the recommended operating voltage range. Do not exceed the absolute maximum voltage rating to avoid over-stressing the input pins.

A fast hysteretic feedback burst control loop monitors (VDD – VEE) and ensures the output voltage is kept within the hysteresis with low overshoots and undershoots during load and line transients. The burst control loop enables efficient operation across full load and allows a wide VOUT adjustability throughout the whole VVIN range. The undervoltage lockout (UVLO) protection monitors the input voltage pin, VIN, with hysteresis and input filter ensuring robust system performance under noisy conditions. The overvoltage lockout (OVLO) protection monitors the input voltage pin, VIN, protects against over-voltage stress by disabling switching and reducing the internal peak voltage. Controlled soft-start timing, provided throughout the full power-up time, limits the peak input inrush current while charging the output capacitor and load.

The UCC14340-Q1 also provides a second output rail, (COM – VEE), that is used as a negative bias for the gate drivers, allowing quicker turn-off switching for the IGBTs, and also to protect from unwanted turn-on during fast switching of SiC devices. (COM – VEE) has a simple, yet fast and efficient bias controller to ensure the positive and negative rails are regulated during the PWM switching. The COM pin can be connected from the source of SiC device or emitter of an IGBT device. An external current limiting resistor allows the designer to program the sink and source current peak according to the needs of the gate drive system.

A fault protection and power-good status pin provides a mechanism for the host controller to monitor the status of the DC/DC converter and provide proper sequencing of power and PWM control signals to the gate driver. Fault protection includes undervoltage, overvoltage, over-temperature shutdown, and isolated channel communication interface watchdog timer.

A typical soft-start ramp-up time is approximately 3 ms, but varies based on input voltage, output voltage, output capacitance, and load. If either output is shorted or over-loaded, the device is not able to power-up within the tSOFT_START_TIME_OUT-ms soft-start watch-dog-timer protection time, so the device latches off for protection. The latch can be reset by toggling the ENA pin or powering VIN down and up.

The output load must be kept low until start-up is complete and PG pin is low. When powering up, do not apply a heavy load to (VDD – VEE) or (COM – VEE) outputs until the PG pin has indicated power is good (pulling logic low) to avoid problems providing the power to ramp-up the voltage.

TI recommends to use the PG status indicator as a trigger point to start the PWM signal into the gate driver. PG output removes any ambiguity as to when the outputs are ready by providing a robust closed loop indication of when both (VDD –VEE) and (COM – VEE) outputs have reached their regulation threshold within ±10%.

Do not allow the host to begin PWM to gate driver until after PG goes low. This action typically occurs less than tSOFT_START_TIME_OUT ms after VVIN > VVIN_UVLOP and ENA goes high. The PG status output indicates the power is good after soft-start of (VDD – VEE) and (COM – VEE) and are within ±10% of regulation.

If the host is not monitoring PG, then ensure that the host does not begin PWM to gate driver until 35 ms after VVIN > VVIN_UVLOP and ENA goes high in order to allow enough time for power to be good after soft-start of VDD and VEE.