JAJSDF0 July   2017 UCC27212A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      標準アプリケーション回路
      2.      伝播遅延 対 電源電圧 T = 25℃
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stages
      2. 8.3.2 Undervoltage Lockout (UVLO)
      3. 8.3.3 Level Shift
      4. 8.3.4 Boot Diode
      5. 8.3.5 Output Stages
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PROPAGATION DELAYS, VDD = VHB = 12 V
TDLFF VLI falling to VLO falling CLOAD = 0 10 16 30 ns
TDHFF VHI falling to VHO falling CLOAD = 0 10 16 30 ns
TDLRR VLI rising to VLO rising CLOAD = 0 10 20 42 ns
TDHRR VHI rising to VHO rising CLOAD = 0 10 20 42 ns
PROPAGATION DELAYS, VDD = VHB = 6.8 V
TDLFF VLI falling to VLO falling CLOAD = 0 10 24 50 ns
TDHFF VHI falling to VHO falling CLOAD = 0 10 24 50 ns
TDLRR VLI rising to VLO rising CLOAD = 0 13 28 57 ns
TDHRR VHI rising to VHO rising CLOAD = 0 13 28 57 ns
DELAY MATCHING, VDD = VHB = 12 V
TMON From HO OFF to LO ON TJ = 25°C 4 9.5 ns
TJ = –40°C to +140°C 4 17 ns
TMOFF From LO OFF to HO ON TJ = 25°C 4 9.5 ns
TJ = –40°C to +140°C 4 17 ns
DELAY MATCHING, VDD = VHB = 6.8 V
TMON From HO OFF to LO ON TJ = 25°C 8 ns
TJ = –40°C to +140°C 8 18 ns
TMOFF From LO OFF to HO ON TJ = 25°C 6 ns
TJ = –40°C to +140°C 6 18 ns
OUTPUT RISE AND FALL TIME, VDD = VHB = 12 V
tR LO rise time CLOAD = 1000 pF, from 10% to 90% 7.8 ns
tR HO rise time CLOAD = 1000 pF, from 10% to 90% 7.8 ns
tF LO fall time CLOAD = 1000 pF, from 90% to 10% 6.0 ns
tF HO fall time CLOAD = 1000 pF, from 90% to 10% 6.0 ns
tR LO, HO CLOAD = 0.1 µF, (3 V to 9 V) 0.36 0.6 µs
tF LO, HO CLOAD = 0.1 µF, (9 V to 3 V) 0.20 0.4 µs
OUTPUT RISE AND FALL TIME, VDD = VHB = 6.8 V
tR LO rise time CLOAD = 1000 pF, from 10% to 90% 9.5 ns
tR HO rise time CLOAD = 1000 pF, from 10% to 90% 13.0 ns
tF LO fall time CLOAD = 1000 pF, from 90% to 10% 9.5 ns
tF HO fall time CLOAD = 1000 pF, from 90% to 10% 13.0 ns
tR LO, HO CLOAD = 0.1 µF, (30% to 70%) 0.45 0.7 µs
tF LO, HO CLOAD = 0.1 µF, (70% to 30%) 0.2 0.5 µs
MISCELLANEOUS
Minimum input pulse width that changes the output 100 ns
Bootstrap diode turnoff time (1)(2) IF = 20 mA, IREV = 0.5 A (3) 20 ns
Extended output pulse when VDD = VHB = 6.8 V, VHS = 100 V, and input pulse width is 100 ns 250 ns
(1) Ensured by design.
(2) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.
(3) Typical values for TA = 25°C.
UCC27212A-Q1 timing_diagram_slusco1.gifFigure 1. Timing Diagram