JAJSNS2A may   2022  – july 2023 UCC27444-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Supply Current
      2. 7.3.2 Input Stage
      3. 7.3.3 Enable Function
      4. 7.3.4 Output Stage
      5. 7.3.5 Low Propagation Delays and Tightly Matched Outputs
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD and Power On Reset
        2. 8.2.2.2 Drive Current and Power Dissipation
      3. 8.2.3 Application Curves
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Drive Current and Power Dissipation

The UCC27444-Q1 driver is capable of delivering 4 A of peak current to a switching power device gate (MOSFET, GaN FET) for a period of several-hundred nanoseconds at VDD = 12 V. High peak current is required to turn ON the device quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground, which repeats at the operating switching frequency of the power device. The power dissipated in the gate driver device package depends on the following factors:

  • Gate charge of the power MOSFET (usually a function of the drive voltage VGS, which is very close to input bias supply voltage VDD due to low VOH drop-out).
  • Switching frequency
  • External gate resistors

Because UCC27444-Q1 features low-quiescent currents and internal logic to eliminate any shoot-through in the output driver stage, their effect on the power dissipation within the gate driver is very small compared to the losses due to switching of the power device.

When a driver device is tested with a discrete capacitive load, calculating the power that is required from the bias supply is fairly simple. The following equation provides an example of the energy that must transfer from the bias supply to charge the capacitor.

Equation 1. GUID-8896AFE6-3B67-4952-B315-99E1A9C2C8D6-low.gif

where

  • CLOAD is the load capacitor.
  • VDD is the bias voltage of the driver.

There is an equal amount of energy dissipated when the capacitor is discharged. This leads to a total power loss, as shown in the following equation example.

Equation 2. GUID-DA06ACAA-AEE8-42A3-9ADA-A009D06D1E0C-low.gif

where

  • fSW is the switching frequency.

With VDD = 12 V, CLOAD = 10 nF and fSW = 300 kHz, the switching power loss is calculated as follows:

Equation 3. GUID-0EB1863E-6C45-4890-871C-D252189BB789-low.gif

The switching load presented by a power MOSFET is converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, the power that must dissipate when charging a capacitor is determined, which by using the equivalence Qg = CLOADVDD is shown in the following equation.

Equation 4. GUID-671E3435-2772-45D4-BF90-AC4CFD5B4EB9-low.gif

Assuming that the UCC27444-Q1device is driving power MOSFET with 60 nC of gate charge (Qg = 60 nC at VDD = 12 V) on each output, the gate charge related power loss is calculated using the equation below.

Equation 5. GUID-1E54F4E9-4A84-453C-BB3E-5257D6E6EFF1-low.gif

This power PG is dissipated in the resistive elements of the circuit when the MOSFET turns on or turns off. Half of the total power is dissipated when the load capacitor is charged during turn-on, and the other half is dissipated when the load capacitor is discharged during turn-off. When no external gate resistor is employed between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external gate resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component). Based on this simplified analysis, the driver power dissipation during switching is calculated as follows:

Equation 6. GUID-F9A6C4FA-F901-45EB-BD22-36ABEE61D708-low.gif

where

  • ROFF = ROL
  • RON (effective resistance of pull-up structure)

The above equation is necessary when the external gate resistor is large enough to reduce the peak current of the driver. In addition to the above gate-charge related power dissipation, dissipation in the driver is related to the power associated with the quiescent bias current consumed by the device to bias all internal circuits such as input stage (with pullup and pulldown resistors), enable, and POR sections. As shown in the electrical characteristics table, the maximum quiescent current is less than 0.6 mA. The power loss due to DC current consumption of the driver internal circuit can be calculated as below.

Equation 7. GUID-33F5117F-6511-4E0A-9A43-F4A21713422D-low.gif

Assuming total internal current consumption to be 0.6 mA (maximum) at bias voltage of 12 V, the DC power loss in the driver is:

Equation 8. GUID-19A7C267-881D-4578-8277-174C0C05DAD2-low.gif

This power loss is insignificant compared to gate charge related power dissipation calculated earlier.

With a 12-V supply, the bias current is estimated as follows, with an additional 0.6-mA overhead for the quiescent consumption:

Equation 9. GUID-DB7CDC73-EA88-4B01-A6A3-8972FA9A2709-low.gif

If the gate driver is used with inductive load, then special attention should be paid to the ringing on each pin of the gate driver device. The ringing should not exceed the recommended operating rating of the pin.