JAJS131H July   2000  – November 2022 UCC28C40 , UCC28C41 , UCC28C42 , UCC28C43 , UCC28C44 , UCC28C45 , UCC38C40 , UCC38C41 , UCC38C42 , UCC38C43 , UCC38C44 , UCC38C45

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft-Start Timing
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Input Bulk Capacitor and Minimum Bulk Voltage
        2. 9.2.2.2  Transformer Turns Ratio and Maximum Duty Cycle
        3. 9.2.2.3  Transformer Inductance and Peak Currents
        4. 9.2.2.4  Output Capacitor
        5. 9.2.2.5  Current Sensing Network
        6. 9.2.2.6  Gate Drive Resistor
        7. 9.2.2.7  VREF Capacitor
        8. 9.2.2.8  RT/CT
        9. 9.2.2.9  Start-Up Circuit
        10. 9.2.2.10 Voltage Feedback Compensation
          1. 9.2.2.10.1 Power Stage Poles and Zeroes
          2. 9.2.2.10.2 Slope Compensation
          3. 9.2.2.10.3 Open-Loop Gain
          4. 9.2.2.10.4 Compensation Loop
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Precautions
        2. 9.4.1.2 Feedback Traces
        3. 9.4.1.3 Bypass Capacitors
        4. 9.4.1.4 Compensation Components
        5. 9.4.1.5 Traces and Ground Planes
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • DGK|8
サーマルパッド・メカニカル・データ
発注情報

9.2 Typical Application

A typical application for the UCC28C42 controller in an off-line flyback converter is shown in Figure 9-3. The controller uses an inner current control loop that contains a small current sense resistor which senses the primary inductor current ramp. This current sense resistor transforms the inductor current waveform to a voltage signal that is input directly into the primary side PWM comparator. This inner loop determines the response to input voltage changes. An outer voltage control loop involves comparing a portion of the output voltage to a reference voltage at the input of an error amplifier. When used in an off-line isolated application, the voltage feedback of the isolated output is accomplished using a secondary-side error amplifier and adjustable voltage reference, such as the TL431. The error signal crosses the primary to secondary isolation boundary using an opto-isolator whose collector is connected to the VREF pin and the emitter is connected to FB. The outer voltage control loop determines the response to load changes.

GUID-E6DD1E28-620B-4E8C-A2AE-DABE12462E5A-low.gif Figure 9-3 Typical Application Design Schematic