JAJSDC3A June   2017  – August 2018 UCC27712

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
      2.      標準的な伝播遅延の比較
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dynamic Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD and Under Voltage Lockout
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Level Shift
      6. 8.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 8.3.7 Parasitic Diode Structure
    4. 8.4 Device Functional Modes
      1. 8.4.1 Minimum Input Pulse Operation
      2. 8.4.2 Output Interlock and Dead Time
      3. 8.4.3 Operation Under 100% Duty Cycle Condition
      4. 8.4.4 Operation Under Negative HS Voltage Condition
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 9.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 9.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
        4. 9.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 9.2.2.5 Selecting Gate Resistor RON/ROFF
        6. 9.2.2.6 Selecting Bootstrap Diode
        7. 9.2.2.7 Estimate the UCC27712 Power Losses (PUCC27712)
        8. 9.2.2.8 Estimating Junction Temperature
        9. 9.2.2.9 Operation With IGBT's
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

Selecting Gate Resistor RON/ROFF

Resistor RON and ROFF are sized to achieve the following:

  • Limit ringing caused by parasitic inductances and capacitances.
  • Limit ringing caused by high voltage/current switching dV/dt, dI/dt, and body diode reverse recovery.
  • Fine-tune gate drive strength to optimize switching loss.
  • Reduce electromagnetic interference (EMI).

As mentioned in Output Stage, the UCC27712 has a pull up structure with a P-channel MOSFET providing a peak source current of 1.8A.

For this example 3.3-Ω resistors for RON and 2.2-Ω resistors for ROFF were selected to provide damping for ringing and ample gate drive current.

Equation 6. UCC27712 qu6_slusce9.gif

Therefore the peak source current can be predicted with:

Equation 7. UCC27712 qu7_slusce9.gif
Equation 8. UCC27712 qu8_slusce9.gif

where

  • RON: External turn-on resistance
  • RGFET_Int: Power transistor internal gate resistance, found in the power transistor datasheet.
  • IO+ = Peak source current. The maximum values between 1.8 A, the UCC27712 peak source current, and the calculated value based on the gate drive loop resistance.

In this example:

Equation 9. UCC27712 qu9_slusce9.gif
Equation 10. UCC27712 qu10_slusce9.gif

Therefore, the high-side and low side peak source current is 1.6 A. Similarly, the peak sink current can be calculated with:

Equation 11. UCC27712 qu11_slusce9.gif
Equation 12. UCC27712 qu12_slusce9.gif

where

  • ROFF: External turn-off resistance
  • VDGATE: The diode forward voltage drop which is in series with ROFF. The diode in this example is an MBRM130L.
  • IO- = Peak sink current. The maximum values between 2.8 A, the UCC27712 peak sink current, and the calculated value based on the gate drive loop resistance.

In this example:

Equation 13. UCC27712 qu13_slusce9.gif
Equation 14. UCC27712 qu14_slusce9.gif