JAJSDR6C August   2017  – February 2022 TIC12400-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Mode Selection
        3. 8.3.8.3 Input Enable Selection
        4. 8.3.8.4 Thresholds Adjustment
        5. 8.3.8.5 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable or Disable and Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check and Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
        1. 8.4.2.1 Standard Polling
        2. 8.4.2.2 Matrix polling
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
        3. 8.4.3.3 VS Measurement
        4. 8.4.3.4 Wetting Current Diagnostic
        5. 8.4.3.5 ADC Self-Diagnostic
    5. 8.5 Programming
      1. 8.5.1 SPI Communication Interface Buses
        1. 8.5.1.1 Chip Select ( CS)
        2. 8.5.1.2 System Clock (SCLK)
        3. 8.5.1.3 Slave In (SI)
        4. 8.5.1.4 Slave Out (SO)
      2. 8.5.2 SPI Sequence
        1. 8.5.2.1 Read Operation
        2. 8.5.2.2 Write Operation
        3. 8.5.2.3 Status Flag
    6. 8.6 Register Maps
    7. 8.7 Programming Guidelines
  9. Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Using TIC12400-Q1 in a 12 V Automotive System
    3. 9.3 Resistor-coded Switches Detection in Automotive Body Control Module
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Using TIC12400-Q1 in a 12 V Automotive System

GUID-FC37CC9E-0FDD-49F2-B43E-47A2562497D6-low.gifFigure 9-1 Typical System Diagram of Battery Connections for TIC12400-Q1

The TIC12400-Q1 is designed to operate with a 12 V automotive system. Figure 9-1 depicts a typical system diagram to show how the device is connected to the battery. Remember to be careful when connecting the battery directly to the device on the VS supply pin (through a reverse-blocking diode) or the input (INX) pins since an automotive battery can be subjected to various transient and over-voltage events. Manufacturers have independently created standards and test procedures in an effort to prevent sensitive electronics from failing due to these events. Recently, combined efforts are made with ISO to develop the ISO 16750-2 standard (Road vehicles — Environmental conditions and testing for electrical and electronic equipment — Part 2: Electrical loads), which describe the possible transients that could occur to an automotive battery and specify test methods to simulate them.

It shall be noted that the TIC12400-Q1 is designed and tested according to the ISO 16750-2 standard. A few voltage stress tests and their test conditions are listed below. Exposing the device to more severe transient events than described by the standard could potentially causes performance degradation and long-term damage to the device.

  • Direct current supply voltage: VBAT, min= 6 V; VBAT, max= 16 V
  • To emulate a jump start event, voltage profile described in Figure 9-2 is used.
    GUID-B373E855-669B-40F5-8A59-56C5346ABB80-low.gifFigure 9-2 Voltage Profile to Test a Jump Start Event
    Table 9-1 Voltage Profile Parameters to Test a Jump Start Event
    ParameterValue
    VBAT, min10.8 V
    VBAT, max24 V
    tr< 10 ms
    t160 s ± 6 s
    tf< 10 ms
    Number of cycles1
  • To emulate a load dump event for an alternator with centralized load dump suppression, voltage profile described below is used. UA and US* are applied directly to VBAT.
    Figure 9-3 Voltage Profile to Test a Load Dump Event with Centralized Load Dump Suppression
    Table 9-2 Voltage Profile Used to Test a Load Dump Event With Centralized Load Dump Suppression
    ParameterValue
    UA13.5 V
    US79 V ≤ US ≤ 101
    US*35 V
    td40 ms ≤ td ≤ 400 ms
    tr< 10 ms
    Number of cycles5 pulses at intervals of 1 min
  • To emulate a cranking event, voltage profile describe below is used. US, US6, and UA are applied directly to VBAT.
    Figure 9-4 Voltage Profile to Test a Cranking Event
    Table 9-3 Voltage Profile Used to Test a Cranking Event
    ParameterValue - Level IValue - Level IIValue - Level IV
    US68 V4.5 V6 V
    US9.5 V6.5 V6.5 V
    UB14 V ± 0.2 V14 V ± 0.2 V14 V ± 0.2 V
    tf5 ms ± 0.5 ms5 ms ± 0.5 ms5 ms ± 0.5 ms
    t615 ms ± 1.5 ms15 ms ± 1.5 ms15 ms ± 1.5 ms
    t750 ms ± 5 ms50 ms ± 5 ms50 ms ± 5 ms
    t81000 ms ± 100 ms10000 ms ± 1000 ms10000 ms ± 1000 ms
    tr40 ms ± 4 ms100 ms ± 10 ms100 ms ± 10 ms