JAJSEM0D February   2018  – April 2024 TUSB1044

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.1
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Custom Alternate Mode
      5. 6.4.5 Linear EQ Configuration
      6. 6.4.6 Adjustable VOD Linear Range and DC Gain
      7. 6.4.7 USB3.1 Modes
    5. 6.5 Programming
      1. 6.5.1 Use The Following Procedure to Write to TUSB1044 I2C Registers:
      2. 6.5.2 Use The Following Procedure to Read the TUSB1044 I2C Registers:
      3. 6.5.3 Use The Following Procedure for Setting a Starting Sub-Address for I2C Reads:
    6. 6.6 Register Maps
      1. 6.6.1 TUSB1044 Registers
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 System Examples
      1. 7.3.1 USB 3.1 only (USB/DP Alternate Mode)
      2. 7.3.2 USB3.1 and 2 lanes of DisplayPort
      3. 7.3.3 DisplayPort Only
      4. 7.3.4 USB 3.1 only (USB/Custom Alternate Mode)
      5. 7.3.5 USB3.1 and 1 Lane of Custom Alt Mode
      6. 7.3.6 USB3.1 and 2 Lane of Custom Alt Mode
      7. 7.3.7 USB3.1 and 4 Lane of Custom Alt Mode
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Timing Requirements

MINNOMMAXUNIT
I2C Timing
fSCLI2C clock frequency1MHz
tBUFBus free time between START and STOP conditions0.5µs
tHDSTAHold time after repeated START condition. After this period, the first clock pulse is generated0.26µs
tLOWLow period of the I2C clock0.5µs
tHIGHHigh period of the I2C clock0.26µs
tSUSTASetup time for a repeated START condition0.26µs
tHDDATData hold time0µs
tSUDATData setup time50ns
tRRise time of both SDA and SCL signals120ns
tFFall time of both SDA and SCL signals20 × (VI2C/5.5 V)120ns
tSUSTOSetup time for STOP condition0.26µs
CBUSCapacitive load for each bus line100pF
HPDIN and CTL1
tCTL1_DEBOUNCECTL1 and HPDIN debounce time when transitioning from H to L. DP lanes will be disabled if low is greater than min value.2.5ms
USB3.1 and DisplayPort mode transition requirement GPIO mode
tGP_USB_4DPMin overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa.  Refer to Figure 5-24µs
Power-on timings
td_pgVCC(MIN) to Internal power good asserted high.  Refer to Figure 5-8500µs
tcfg_suCFG pins setup.  Refer to Figure 5-8350µs
tcfg_hdCFG pin hold.  Refer to Figure 5-810µs
tctl_dbCTL[1:0] and FLIP pin debounce.  Refer to Figure 5-816ms
tVCC_RAMPVCC supply ramp requirement.  Refer to Figure 5-80.1100ms
GUID-5298F378-4870-4B97-B42A-EF128F7CB995-low.gifFigure 5-1 I2C Timing Diagram Definitions
GUID-C935245F-812D-44E6-A926-868D3E01C285-low.gifFigure 5-2 USB3.1 to 4-Lane DisplayPort in GPIO Mode
GUID-F34C816B-EC55-4E9B-812D-B2CA37DE3DD1-low.gifFigure 5-3 Propagation Delay
GUID-372ED6BD-25EB-4DA7-87A8-8D4AAC0CF058-low.gifFigure 5-4 Electrical Idle Mode Exit and Entry Delay
GUID-EB249537-7FE8-4925-B3A9-B07EE80C7D83-low.gifFigure 5-5 Output Rise and Fall Times
GUID-448EE96D-EB32-4485-B38F-2CEAC5692EC3-low.gifFigure 5-6 AUX to SBU Switch ON Timing Diagram
GUID-6CA77B1C-D83A-4137-81B5-14EF260BC7BD-low.gifFigure 5-7 AUX to SBU Switch OFF Timing Diagram
GUID-CE61168B-1387-4D00-9E22-AFE78BE9F070-low.gifFigure 5-8 Power-Up Timing Diagram