JAJSFQ0A July   2018  – November 2018 DAC61408 , DAC71408 , DAC81408

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Digital-to-Analog Converters (DACs) Architecture
        1. 10.3.1.1 DAC Transfer Function
        2. 10.3.1.2 DAC Register Structure
          1. 10.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 10.3.1.2.2 Broadcast DAC Register
          3. 10.3.1.2.3 Clear DAC Operation
      2. 10.3.2 Internal Reference
      3. 10.3.3 Device Reset Options
        1. 10.3.3.1 Power-on-Reset (POR)
        2. 10.3.3.2 Hardware Reset
        3. 10.3.3.3 Software Reset
      4. 10.3.4 Thermal Protection
        1. 10.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 10.3.4.2 Thermal Shutdown
    4. 10.4 Device Functional Modes
      1. 10.4.1 Toggle Mode
      2. 10.4.2 Differential Mode
      3. 10.4.3 Power-Down Mode
    5. 10.5 Programming
      1. 10.5.1 Stand-Alone Operation
        1. 10.5.1.1 Streaming Mode Operation
      2. 10.5.2 Daisy-Chain Operation
      3. 10.5.3 Frame Error Checking
    6. 10.6 Register Maps
      1. 10.6.1  NOP Register (Offset = 00h) [reset = 0000h]
        1. Table 9. NOP Register Field Descriptions
      2. 10.6.2  DEVICEID Register (Offset = 01h) [reset = ----h]
        1. Table 10. DEVICEID Register Field Descriptions
      3. 10.6.3  STATUS Register (Offset = 02h) [reset = 0000h]
        1. Table 11. STATUS Register Field Descriptions
      4. 10.6.4  SPICONFIG Register (Offset = 03h) [reset = 0A24h]
        1. Table 12. SPICONFIG Register Field Descriptions
      5. 10.6.5  GENCONFIG Register (Offset = 04h) [reset = 7F00h]
        1. Table 13. GENCONFIG Register Field Descriptions
      6. 10.6.6  BRDCONFIG Register (Offset = 05h) [reset = FFFFh]
        1. Table 14. BRDCONFIG Register Field Descriptions
      7. 10.6.7  SYNCCONFIG Register (Offset = 06h) [reset = 0000h]
        1. Table 15. SYNCCONFIG Register Field Descriptions
      8. 10.6.8  TOGGCONFIG0 Register (Offset = 07h) [reset = 0000h]
        1. Table 16. TOGGCONFIG0 Register Field Descriptions
      9. 10.6.9  TOGGCONFIG1 Register (Offset = 08h) [reset = 0000h]
        1. Table 17. TOGGCONFIG1 Register Field Descriptions
      10. 10.6.10 DACPWDWN Register (Offset = 09h) [reset = FFFFh]
        1. Table 18. DACPWDWN Register Field Descriptions
      11. 10.6.11 DACRANGEn Register (Offset = 0Bh - 0Ch) [reset = 0000h]
        1. Table 19. DACRANGEn Register Field Descriptions
      12. 10.6.12 TRIGGER Register (Offset = 0Eh) [reset = 0000h]
        1. Table 20. TRIGGER Register Field Descriptions
      13. 10.6.13 BRDCAST Register (Offset = 0Fh) [reset = 0000h]
        1. Table 21. BRDCAST Register Field Descriptions
      14. 10.6.14 DACn Register (Offset = 14h - 1Bh) [reset = 0000h]
        1. Table 22. DACn Register Field Descriptions
      15. 10.6.15 OFFSETn Register (Offset = 21h - 22h) [reset = 0000h]
        1. Table 23. OFFSETn Register Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure for Remote Ground Tracking
        1. 11.2.2.1 Generating 300mV Offset
        2. 11.2.2.2 Amplifier Selection
        3. 11.2.2.3 Passive Component Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
    2. 14.2 関連リンク
    3. 14.3 ドキュメントの更新通知を受け取る方法
    4. 14.4 コミュニティ・リソース
    5. 14.5 商標
    6. 14.6 静電気放電に関する注意事項
    7. 14.7 Glossary
  15. 15メカニカル、パッケージ、および注文情報

10.5.2 Daisy-Chain Operation

For systems that contain more than one DACx1408 devices, the SDO pin can be used to daisy-chain them together. The SDO pin must be enabled by setting the SDO-EN bit before initiating the daisy-chain operation. Daisy-chain operation is useful in reducing the number of serial interface lines.

The first falling edge on the CS pin starts the operation cycle. If more than 24 SCLK pulses are applied while the CS pin is kept low, the data ripples out of the shift register and is clocked out on the SDO pin either on the falling edge or rising edge of SCLK according to the FSDO bit. By connecting the SDO output of the first device to the SDI input of the next device in the chain, a multiple-device interface is constructed. Each device in the system requires 24 clock pulses. As a result the total number of clock cycles must be equal to 24 × N, where N is the total number of DACx1408 devices in the daisy chain. When the serial transfer to all devices is complete the CS signal is taken high. This action transfers the data from the SPI shift registers to the internal registers of each device in the daisy chain and prevents any further data from being clocked into the input shift register. Daisy-chain operation is not supported while in streaming mode.

DAC81408 DAC71408 DAC61408 DAC1408-daisychain-slaser3.gifFigure 51. Daisy-Chain Layout