JAJSG29A August   2018  – October 2018 TPS7B70-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Enable (EN)
      2. 7.3.2 Adjustable Power-Good Threshold (PG, PGADJ)
      3. 7.3.3 Adjustable Power-Good Delay Timer (DELAY)
      4. 7.3.4 Undervoltage Shutdown
      5. 7.3.5 Current Limit
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With Input Voltage Less Than 4 V
      2. 7.4.2 Operation With Input Voltage Greater Than 4 V
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
        3. 8.2.2.3 Power-Good Threshold
        4. 8.2.2.4 Power-Good Delay, t(DLY)
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 14 V, COUT ≥ 4.7 µF, and 1 mΩ < ESR < 20 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT (IN)
I(SLEEP) Input sleep current EN = off 4.5 µA
I(GND) Input quiescent current VIN = VOUT + 1 V to 40 V, EN = on, VINT > 2 V, IOUT < 1 mA, –40°C ≤ TJ ≤ 85°C 19 29.6 µA
V(UVLO) Undervoltage lockout, falling Ramp VIN down until output is turned off 2.6 V
V(UVLO_HYST) UVLO hysteresis 0.5 V
ENABLE INPUT (EN)
VIL Low-level input voltage 0.7 V
VIH High-level input voltage 2 V
Vhys Hysteresis 150 mV
REGULATED OUTPUT (OUT)
VOUT Regulated output VIN = VOUT + 1 V to 40 V, IOUT = 0 mA to 300 mA, –40°C ≤ TJ ≤ 125°C –2% 2%
VIN = VOUT + 1 V to 40 V, IOUT = 0 mA to 300 mA –2.5% 2.5%
ΔVOUT(ΔVIN) Line regulation VIN = VOUT + 1 V to 40 V, IOUT = 1 mA 10 mV
ΔVOUT(ΔIOUT) Load regulation IOUT = 1 mA to 300 mA 20 mV
V(dropout) Dropout voltage (VIN – VOUT)(1)(2) IOUT = 300 mA 300 400 mV
IOUT = 200 mA 170 325
I(LIM) Output current limit VOUT shorted to ground, VIN = 5.6 V 301 680 1000 mA
PSRR Power-supply ripple rejection(3) IOUT = 100 mA, COUT = 10 µF, frequency (f) = 100 Hz 60 dB
IOUT = 100 mA, COUT = 10 µF, frequency (f) = 100 kHz 40
POWER GOOD (PG, PGADJ)
VOL(PG) PG output, low voltage IOL = 5 mA, PG pulled low 0.4 V
Ilkg(PG) PG pin leakage current PG pulled to VOUT through a 10‑kΩ resistor 1 µA
V(PG_TH) Default power-good threshold VOUT powered above the internally set tolerance, PGADJ pin shorted to ground 88.6 91.6 93.6 % of VOUT
V(PG_HYST) Power-good hysteresis VOUT falling below the internally set tolerance hysteresis 2 % of VOUT
PGADJ
V(PGADJ_TH) Switching voltage for the power-good adjust pin VOUT is falling 1.067 1.1 1.133 V
POWER-GOOD DELAY
I(DLY_CHG) DELAY capacitor charging current 3 5 10 µA
V(DLY_TH) DELAY pin threshold to release PG high Voltage at DELAY pin is ramped up 0.95 1 1.05 V
I(DLY_DIS) DELAY capacitor discharging current VDELAY = 1 V 0.5 mA
TEMPERATURE
T(SD) Junction shutdown temperature 175 °C
T(HYST) Hysteresis of thermal shutdown 25 °C
(1) This test is done with VOUT in regulation, measuring the VIN – VOUT when VOUT drops by 100 mV from the rated output voltage at the specified load.
(2) Dropout is not measured for VOUT = 3.3 V in this test because VIN must be 4 V or greater for proper operation.
(3) Design information—not tested, determined by characterization.