JAJSGA9C September   2018  – September 2019 ISO1500

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     概略回路図
  4. 改訂履歴
  5. 概要 (続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: Driver
    10. 7.10 Electrical Characteristics: Receiver
    11. 7.11 Supply Current Characteristics: Side 1(ICC1)
    12. 7.12 Supply Current Characteristics: Side 2(ICC2)
    13. 7.13 Switching Characteristics: Driver
    14. 7.14 Switching Characteristics: Receiver
    15. 7.15 Insulation Characteristics Curves
    16. 7.16 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 9.3.2 Failsafe Receiver
      3. 9.3.3 Thermal Shutdown
      4. 9.3.4 Glitch-Free Power Up and Power Down
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Data Rate and Bus Length
        2. 10.2.2.2 Stub Length
        3. 10.2.2.3 Bus Loading
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

Failsafe Receiver

The differential receiver of the ISO1500 device has failsafe protection from invalid bus states caused by:

  • Open bus conditions such as a broken cable or a disconnected connector
  • Shorted bus conditions such as insulation breakdown of a cable that shorts the twisted-pair
  • Idle bus conditions that occur when no driver on the bus is actively driving

The differential input of the RS-485 receiver is 0 in any of these conditions for a terminated transmission line. The receiver outputs a failsafe logic-high state so that the output of the receiver is not indeterminate.

The receiver thresholds are offset in the receiver failsafe protection so that the indeterminate range of the input does not include a 0 V differential. The receiver output must generate a logic high when the differential input (VID) is greater than 200 mV to comply with the RS-485 standard. The receiver output must also generate a output a logic low when VID is less than –200 mV to comply with the RS-485 standard. The receiver parameters that determine the failsafe performance are VTH+, VTH–, and VHYS. Differential signals less than –200 mV always cause a low receiver output as shown in the Electrical Characteristics table. Differential signals greater than 200 mV always cause a high receiver output. A differential input signal that is near zero is still greater than the VTH+ threshold which makes the receiver output logic high. The receiver output goes to a low state only when the differential input decreases by VHYS to less than VTH+.

The internal failsafe biasing feature removes the need for the two external resistors that are typically required with traditional isolated RS-485 transceivers as shown in Figure 29.

ISO1500 iso1500-failsafe-transceiver.gifFigure 29. Failsafe Transceiver