JAJSHR0E March   2017  – July 2022 LMH1297

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. 概要 (続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended SMBus Interface Timing Specifications
    7. 7.7 Serial Parallel Interface (SPI) Timing Specifications
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  4-Level Input Pins and Thresholds
      2. 8.3.2  Equalizer (EQ) and Cable Driver (CD) Mode Control
        1. 8.3.2.1 EQ/CD_SEL Control
        2. 8.3.2.2 OUT0_SEL and SDI_OUT_SEL Control
      3. 8.3.3  Input Carrier Detect
      4. 8.3.4  –6-dB Splitter Mode Launch Amplitude for SDI_IO+ (EQ Mode Only)
      5. 8.3.5  Continuous Time Linear Equalizer (CTLE)
        1. 8.3.5.1 Line-Side Adaptive Cable Equalizer (SDI_IO+ in EQ mode)
        2. 8.3.5.2 Host-Side Adaptive PCB Trace Equalizer (IN0± in CD Mode)
      6. 8.3.6  Clock and Data (CDR) Recovery
      7. 8.3.7  Internal Eye Opening Monitor (EOM)
      8. 8.3.8  Output Function Control
      9. 8.3.9  Output Driver Control
        1. 8.3.9.1 Line-Side Output Cable Driver (SDI_IO+ in CD mode, SDI_OUT+ in EQ or CD mode)
          1. 8.3.9.1.1 Output Amplitude (VOD)
          2. 8.3.9.1.2 Output Pre-Emphasis
          3. 8.3.9.1.3 Output Slew Rate
          4. 8.3.9.1.4 Output Polarity Inversion
        2. 8.3.9.2 Host-Side 100-Ω Output Driver (OUT0± in EQ or CD mode)
      10. 8.3.10 Status Indicators and Interrupts
        1. 8.3.10.1 LOCK_N (Lock Indicator)
        2. 8.3.10.2 CD_N (Carrier Detect)
        3. 8.3.10.3 INT_N (Interrupt)
      11. 8.3.11 Additional Programmability
        1. 8.3.11.1 Cable EQ Index (CEI)
        2. 8.3.11.2 Digital MUTEREF
    4. 8.4 Device Functional Modes
      1. 8.4.1 System Management Bus (SMBus) Mode
        1. 8.4.1.1 SMBus Read and Write Transaction
          1. 8.4.1.1.1 SMBus Write Operation Format
          2. 8.4.1.1.2 SMBus Read Operation Format
      2. 8.4.2 Serial Peripheral Interface (SPI) Mode
        1. 8.4.2.1 SPI Read and Write Transactions
        2. 8.4.2.2 SPI Write Transaction Format
        3. 8.4.2.3 SPI Read Transaction Format
        4. 8.4.2.4 SPI Daisy Chain
    5. 8.5 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SMPTE Requirements and Specifications
      2. 9.1.2 Low-Power Optimization in CD Mode
      3. 9.1.3 Optimized Loop Bandwidth Settings for Arria 10 FPGA Applications
    2. 9.2 Typical Applications
      1. 9.2.1 Bidirectional I/O
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Cable Equalizer With Loop-Through
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Stack-Up and Ground References
      2. 11.1.2 High-Speed PCB Trace Routing and Coupling
        1. 11.1.2.1 SDI_IO± and SDI_OUT±:
        2. 11.1.2.2 IN0± and OUT0±:
      3. 11.1.3 Anti-Pads
      4. 11.1.4 BNC Connector Layout and Routing
      5. 11.1.5 Power Supply and Ground Connections
      6. 11.1.6 Footprint Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER
PDEQ_MODEPower dissipation, EQ Mode,
Measured with PRBS10,
CDR Locked to 11.88 Gbps,
VOD = default,
HEO/VEO lock monitor disabled
SDI_OUT± disabled
OUT0± enabled
275mW
SDI_OUT± enabled
OUT0± enabled
418mW
PDCD_MODEPower dissipation, CD Mode,
Measured with PRBS10,
CDR Locked to 11.88 Gbps,
VOD = default,
HEO/VEO lock monitor disabled
SDI_IO± enabled
SDI_OUT± disabled
OUT0± disabled
305mW
SDI_IO± enabled
SDI_OUT± disabled
OUT0± enabled
350mW
SDI_IO± enabled
SDI_OUT± enabled
OUT0± disabled
442mW
SDI_IO± enabled
SDI_OUT± enabled
OUT0± enabled
485mW
PDZPower dissipation,
Power Save Mode
EQ Mode, Power Save Mode,
ENABLE = H, no signal applied at SDI_IO+
25mW
CD Mode, Power Save Mode,
ENABLE = H, no signal applied at IN0±
25mW
IDDEQ_MODECurrent consumption, EQ Mode,
Measured with PRBS10,
CDR Locked to 11.88 Gbps,
VOD = default,
HEO/VEO lock monitor disabled
SDI_OUT± disabled
OUT0± enabled
110137mA
SDI_OUT± enabled
OUT0± enabled
167200mA
IDDCD_MODECurrent consumption, CD Mode,
Measured with PRBS10,
CDR Locked to 11.88 Gbps,
VOD = default,
HEO/VEO lock monitor disabled
SDI_IO± enabled
SDI_OUT± disabled
OUT0± disabled
122146mA
SDI_IO± enabled
SDI_OUT± disabled
OUT0± enabled
140166mA
SDI_IO± enabled
SDI_OUT± enabled
OUT0± disabled
177211mA
SDI_IO± enabled
SDI_OUT± enabled
OUT0± enabled
194230mA
IDDZCurrent consumption,
Power Save Mode
EQ Mode, Power Save Mode,
ENABLE = H, no signal applied at SDI_IO+
10mA
CD Mode, Power Save Mode,
ENABLE = H, no signal applied at IN0±
10mA
IDDZ_PDCurrent consumption,
Power-Down Mode
EQ Mode, Power-Down Mode,
ENABLE = L, no signal applied at SDI_IO+
1030mA
CD Mode, Power-Down Mode,
ENABLE = L, no signal applied at IN0±
1030
IDDTRANS_EQCurrent consumption, EQ Mode
CDR acquiring lock to 11.88 Gbps,
VOD = default,
HEO/VEO lock monitor enabled
SDI_OUT± disabled
OUT0± enabled
205mA
SDI_OUT± enabled
OUT0± enabled
260mA
IDDTRANS_CDCurrent consumption, CD Mode
CDR acquiring lock to 11.88 Gbps,
VOD = default,
HEO/VEO lock monitor enabled
SDI_IO± enabled
SDI_OUT± disabled
OUT0± disabled
200mA
SDI_IO± enabled
SDI_OUT± disabled
OUT0± enabled
225mA
SDI_IO± enabled
SDI_OUT± enabled
OUT0± disabled
271mA
SDI_IO± enabled
SDI_OUT± enabled
OUT0± enabled
290mA
LVCMOS DC SPECIFICATIONS
VIHLogic high input voltage2-level input (SS_N, SCK, MOSI, EQ/CD_SEL, SDI_OUT_SEL, OUT0_SEL, ENABLE)0.72 × VINVIN + 0.3V
2-level input (SCL, SDA)0.7 × VIN3.6V
VILLogic low input voltage2-level input (SS_N, SCK, MOSI, EQ/CD_SEL, SDI_OUT_SEL, OUT0_SEL, ENABLE, SCL, SDA)00.3 × VINV
VOHLogic high output voltageIOH = –2 mA, (MISO)0.8 × VINVINV
VOLLogic low output voltageIOL = 2 mA, (MISO)00.2 × VINV
IOL = 3 mA, (LOCK_N, SDA)0.4V
IIHInput high leakage current
(Vinput = VIN)
LVCMOS (EQ/CD_SEL, SDI_OUT_SEL, ENABLE)15µA
LVCMOS (OUT0_SEL)65µA
LVCMOS (LOCK_N)10µA
SPI mode: LVCMOS (SS_N, SCK, MOSI)15µA
SMBus mode: LVCMOS (SCL, SDA)10µA
IILInput low leakage current
(Vinput = GND)
LVCMOS (EQ/CD_SEL, SDI_OUT_SEL, ENABLE)–50µA
LVCMOS (OUT0_SEL)–15µA
LVCMOS (LOCK_N)–10µA
SPI mode: LVCMOS (SCK, MOSI)–15µA
SPI mode: LVCMOS (SS_N)–50µA
SMBus mode: LVCMOS (SCL, SDA)–10µA
4-LEVEL LOGIC DC SPECIFICATIONS (APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)
VLVL_HLEVEL-H input voltageMeasured voltage at 4-level pin with external 1 kΩ to VINVINV
VLVL_FLEVEL-F default voltageMeasured voltage 4-level pin at default2/3 × VINV
VLVL_RLEVEL-R input voltageMeasured voltage at 4-level pin with external 20 kΩ to VSS1/3 × VINV
VLVL_LLEVEL-L input voltageMeasured voltage at 4-level pin with external 1 kΩ to VSS0V
IIHInput high leakage current
(Vinput = VIN)
4-levels (HOST_EQ0, MODE_SEL, OUT_CTRL, SDI_VOD)204580µA
SMBus mode: 4-levels (ADDR0, ADDR1)204580µA
IILInput low leakage current
(Vinput = GND)
4-levels (HOST_EQ0, MODE_SEL, OUT_CTRL, SDI_VOD)–160–93–40µA
SMBus mode: 4-levels (ADDR0, ADDR1)–160–93–40µA
RECEIVER SPECIFICATIONS (SDI_IO+, EQ MODE)
RSDI_IO_TERMDC input single-ended terminationSDI_IO+ and SDI_IO– to internal common mode bias637587Ω
RLSDI_IO_S11Input return loss at SDI_IO+ reference to 75 Ω(1)S11, 5 MHz to 1.485 GHz–30dB
S11, 1.485 GHz to 3 GHz–22dB
S11, 3 GHz to 6 GHz–12dB
S11, 6 GHz to 12 GHz–8dB
VSDI_IO_CMSDI_IO+ DC common-mode voltageInput DC common-mode voltage at SDI_IO+ or SDI_IO- to GND1.4V
VSDI_IO_WANDERInput DC wanderSD, input signal at SDI_IO+,
Input launch amplitude = 800 mVp-p
100mVp-p
HD, 3G, 6G, 12G, input signal at SDI_IO+,
Input launch amplitude = 800 mVp-p
50mVp-p
RECEIVER SPECIFICATIONS (IN0±, CD MODE)
RIN0_TERMDC input differential terminationMeasured across IN0+ to IN0–80100120Ω
RLIN0_SDD11Input differential return loss(1)SDD11, 10 MHz – 2.8 GHz–22dB
SDD11, 2.8 GHz – 6 GHz–16dB
SDD11, 6 GHz – 11.1 GHz–10dB
RLIN0_SCD11Differential to common-mode input conversion(1)SCD11, 10 MHz to 11.1 GHz–21dB
VIN0_CMDC common-mode voltageInput common-mode voltage at IN0+ or IN0– to GND2.06V
CDON_IN0Signal detect (default)
Assert ON threshold level for IN0±
11.88 Gbps PRBS10 pattern20mVp-p
CDOFF_IN0Signal detect (default)
Deassert OFF threshold level for IN0±
11.88 Gbps PRBS10 pattern18mVp-p
DRIVER OUTPUT (SDI_IO+ AND SDI_OUT+, CD MODE)
ROUT_TERMDC output single-ended terminationSDI_IO+ and SDI_IO–,
SDI_OUT+ and SDI_OUT– to VIN
637587Ω
VODCD_OUTPOutput single-ended output voltageMeasure AC signal at SDI_IO+ and SDI_OUT+, with SDI_IO– and SDI_OUT– AC terminated with 75 Ω
SDI_VOD = H
840mVp-p
SDI_VOD = F720800880mVp-p
SDI_VOD = R880mVp-p
SDI_VOD = L760mVp-p
VODCD_OUTNOutput single-ended output voltageMeasure AC signal at SDI_IO– and SDI_OUT-, with SDI_IO+ and SDI_OUT+ AC terminated with 75 Ω
SDI_VOD = H
840mVp-p
SDI_VOD = F720800880mVp-p
SDI_VOD = R880mVp-p
SDI_VOD = L760mVp-p
PRECD_OUTPOutput pre-emphasisOutput pre-emphasis boost amplitude at SDI_IO+ and SDI_OUT+, programmed to maximum setting through register, measured at SDI_VOD=F2dB
PRECD_OUTNOutput pre-emphasisOutput pre-emphasis boost amplitude at SDI_IO– and SDI_OUT–, programmed to maximum setting through register, measured at SDI_VOD=F2dB
tR_F_SDIOutput rise and fall time(1)Measured with PRBS10 pattern, default VOD at 20% – 80% amplitude, default pre-emphasis enabled
11.88 Gbps
3442ps
5.94 Gbps3643ps
2.97 Gbps5967ps
1.485 Gbps6073ps
270 Mbps400550700ps
tR_F_DELTAOutput rise and fall time mismatch(1)Measured with PRBS10 pattern, default VOD at 20% – 80% amplitude, default pre-emphasis enabled
11.88 Gbps
318ps
5.94 Gbps2.712ps
2.97 Gbps0.811ps
1.485 Gbps0.812ps
270 Mbps72150ps
VOVERSHOOTOutput overshoot or undershoot(1)Measured with PRBS10 pattern, default VOD, default pre-emphasis enabled(3)
12G/6G/3G/HD/SD
5%
VDC_OFFSETDC offset12G/6G/3G/HD/SD±0.2V
VDC_WANDERDC wander3G/HD/SD with EQ pathological pattern20mV
RLCD_S22Output return loss at SDI_IO+ and SDI_OUT+ reference to 75 Ω(1)S22, 5 MHz to 1.485 GHz–25dB
S22, 1.485 GHz to 3 GHz–22dB
S22, 3 GHz to 6 GHz–12dB
S22, 6 GHz to 12 GHz–8dB
DRIVER OUTPUT (OUT0±, EQ AND CD MODE)
ROUT0_TERMDC output differential terminationMeasured across OUT0+ and OUT0–80100120Ω
VODOUT0Output differential voltage at OUT0±Measured with 8T pattern
HOST_EQ0 = H
410mVp-p
HOST_EQ0 = F485560620mVp-p
HOST_EQ0 = R635mVp-p
HOST_EQ0 = L810mVp-p
VODOUT0_DEDe-emphasized output differential voltage at OUT0±Measured with 8T pattern
HOST_EQ0 = H
410mVp-p
HOST_EQ0 = F550mVp-p
HOST_EQ0 = R545mVp-p
HOST_EQ0 = L532mVp-p
tR/tFOutput rise and fall timeMeasured with 8T Pattern, 20% – 80% amplitude45ps
RLOUT0-SDD22Output differential return loss(1)Measured with the device powered up and outputs a 10-MHz clock signal
SDD22, 10 MHz – 2.8 GHz
–24dB
SDD22, 2.8 GHz – 6 GHz–16dB
SDD22, 6 GHz – 11.1 GHz–15dB
RLOUT0-SCC22Output common-mode return loss(1)Measured with the device powered up and outputs a 10-MHz clock signal.
SCC22, 10 MHz – 4.75 GHz
–12dB
SCC22, 4.75 GHz – 11.1 GHz–9dB
VOUT0_CMAC common-mode voltage on OUT0±(1)Default setting, PRBS31, 11.88 Gbps8mV (rms)
RECLOCKER OUTPUT JITTER (EQ MODE)
TJEQ_MODETotal jitter, reclocked output(1)(2)Measured at OUT0±, with SDI_OUT disabled (BER ≤ 1E-12), PRBS10,
TX launch amplitude = 800 mVp-p before cable to SDI_IO+
11.88 Gbps: 75-m Belden 1694A
0.140.18UIp-p
5.94 Gbps: 120-m Belden 1694A0.1
2.97 Gbps: 200-m Belden 1694A0.1
1.485 Gbps: 300-m Belden 1694A0.1
270 Mbps: 600-m Belden 1694A0.11
TJRAWTotal jitter, with CDR bypassedMeasured at OUT0±, with SDI_OUT disabled (BER ≤ 1E-12), PRBS10,
TX launch amplitude = 800 mVp-p before cable to SDI_IO+
125 Mbps: 600-m Belden 1694A
0.2UIp-p
RECLOCKER OUTPUT JITTER (CD MODE)
AJCD_MODEAlignment jitter(1)Measured at SDI_IO+ and SDI_OUT+, OUT0± disabled
PRBS10, 3G/HD/SD12G/6G/3G/HD/SD
0.10.14UI
TMJCD_MODETiming jitter(1)Measured at SDI_IO+ and SDI_OUT+, OUT0± disabled
PRBS10, 12G/6G/3G/HD/SD
0.45UI
RECLOCKER SPECIFICATIONS (EQ MODE UNLESS OTHERWISE SPECIFIED)
LOCKRATEReclocker lock data ratesSMPTE 12G, /111.88Gbps
SMPTE 12G, /1.00111.868Gbps
SMPTE 6G, /15.94Gbps
SMPTE 6G, /1.0015.934Gbps
SMPTE 3G, /12.97Gbps
SMPTE 3G, /1.0012.967Gbps
SMPTE HD, /11.485Gbps
SMPTE HD, /1.0011.4835Gbps
SMPTE SD, /1270Mbps
BYPASSRATEReclocker automatically goes to bypassMADI125Mbps
BWPLLPLL BandwidthApplied 0.2 UI input sinusoidal jitter, measure –3-dB bandwidth on input-to-output jitter transfer
11.88 Gbps
13MHz
5.94 Gbps7MHz
2.97 Gbps5MHz
1.485 Gbps3MHz
270 Mbps1MHz
JPEAKINGPLL jitter peaking11.88 Gbps, 5.94 Gbps, 2.97 Gbps,
1.485 Gbps, 270 Mbps
<0.3dB
JTOL_INSDI_IO+ input jitter toleranceSinusoidal jitter tolerance,
tested at 3G, 6G and 12G,
SJ amplitude swept from 1 MHz to 80 MHz, tested at BER ≤ 1E-12, cable equalizer at SDI_IO+ bypassed
0.65UI
TLOCKLock timeSMPTE supported data rates, disable HEO/VEO monitor, cable equalizer at SDI_IO+ bypassed5ms
TADAPTEQ adapt time at EQ ModeAdaptation time for cable equalizer at SDI_IO+, reclocker bypassed5ms
TEMPLOCKVCO temperature lock rangeMeasured with temperature ramp of 5°C per min, ramp up and down, –40°C to 85°C operating range at 11.88 Gbps125°C
TLATEQ_MODEReclocker latency at EQ ModeMeasured from SDI_IO+ to OUT0, 11.88 Gbps, SDI_IO+, 75-m Belden 1694A at SDI_IO+1.4 UI + 465ps
Measured from SDI_IO+ to SDI_OUT+, 11.88 Gbps, SDI_IO+, 75-m Belden 1694A at SDI_IO+1.7 UI + 415ps
TLATCD_MODEReclocker latency at CD ModeMeasured from IN0± to SDI_IO+, 11.88 Gbps1.5 UI + 175ps
Measured from IN0± to SDI_OUT+, 11.88 Gbps1.6 UI + 130ps
This parameter is measured with the LMH1297EVM (Evaluation board for LMH1297).
This limit is ensured by bench characterization and is not production tested.
VOVERSHOOT overshoot/undershoot maximum measurements are largely affected by the PCB layout and input test pattern. The maximum value specified in Section 7.5 for VOVERSHOOT is based on bench evaluation across temperature and supply voltages with the LMH1297EVM.