JAJSOG4C July   2007  – April 2022 PCA9306-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. 概要 (続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: Translating Down, VIH = 3.3 V
    7. 7.7  Switching Characteristics: Translating Down, VIH = 2.5 V
    8. 7.8  Switching Characteristics: Translating Up, VIH = 2.3 V
    9. 7.9  Switching Characteristics: Translating Up, VIH = 1.5 V
    10. 7.10 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Definition of threshold voltage
      2. 9.1.2 Correct Device Set Up
      3. 9.1.3 Disconnecting a Target from the Main I2C Bus Using the EN Pin
      4. 9.1.4 Supporting Remote Board Insertion to Backplane with PCA9306-Q1
      5. 9.1.5 Switch Configuration
      6. 9.1.6 Controller on Side 1 or Side 2 of Device
      7. 9.1.7 LDO and PCA9306-Q1 Concerns
      8. 9.1.8 Current Limiting Resistance on VREF2
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable (EN) Pin
      2. 9.3.2 Voltage Translation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 General Applications of I2C
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Bidirectional Translation
        2. 10.2.2.2 Sizing Pullup Resistor
        3. 10.2.2.3 PCA9306-Q1 Bandwidth
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

LDO and PCA9306-Q1 Concerns

The VREF1 pin can be supplied by a low-dropout regulator (LDO), but in some cases the LDO can lose its regulation because of the bias current from VREF2 to VREF1. If the LDO cannot sink the bias current, then the current has no other paths to ground and instead charges up the capacitance on the VREF1 node (both external and parasitic). This results in an increase in voltage on the VREF1 node. If no other paths for current to flow are established (such as back biasing of body diodes or clamping diodes through other devices on the VREF1 node), then the VREF1 voltage ends up stabilizing when Vgs of the pass FET is equal to Vth. This means VREF1 node voltage is VCC2 - Vth. Note that any target or controllers running off of the LDO now see the VCC2 - Vth voltage which may cause damage to those target or controllers if they are not rated to handle the increased voltage.

GUID-645BF4F6-D8A7-4781-8D4F-7970224BF01D-low.gifFigure 9-8 Example of no leakage current path when using LDO

To ensure LDO does not lose regulation due to the bias current of PCA9306-Q1, a weak pull down resistor can be placed on VREF1 to ground to provide a path for the bias current to travel. The recommended pull down resistor is calculated by Equation 4 where 0.75 gives about 25% margin for error incase bias current increases during operation.

GUID-A4179B70-C511-4487-821C-8C561DFEF4D1-low.gifFigure 9-9 Example with Leakage current path when using an LDO
Equation 1. Ven = VREF1 + Vth

where

  • Vth is approximately 0.6 V
Equation 2. Ibias = (VCC2 - Ven)/200k
Equation 3. Rpulldown = VOUT/Ibias
Equation 4. Recommended Rpulldown = Rpulldown x 0.75