JAJU881 December   2022

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 Devices
        1. 2.3.1.1 AWR2243
        2. 2.3.1.2 AM2732R
        3. 2.3.1.3 LP876242-Q1
        4. 2.3.1.4 LM62460-Q1
        5. 2.3.1.5 TCAN1043A-Q1
        6. 2.3.1.6 TCAN1044A-Q1
        7. 2.3.1.7 DP83TC812-Q1
        8. 2.3.1.8 TPS61379-Q1
        9. 2.3.1.9 TMP102-Q1
  8. 3System Design Theory
  9. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Test Setup
      1. 4.2.1 Virtual Antenna Array
    3. 4.3 Test Results
      1. 4.3.1 Angle Resolution Measurement
  10. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout Recommendations
        1. 5.1.3.1 20 GHz (FMCW) RF LO Sync
        2. 5.1.3.2 PCB Layer Stackup
        3. 5.1.3.3 Board Photos
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 サポート・リソース
    5. 5.5 Trademarks

3 System Design Theory

For systems with additional safety requirements, diagnostic and monitoring features have been included in this reference design.

  • Imaging radar
  • Watchdog: The LP876242-Q1 device includes a Q&A watchdog to monitor software lockup, and a system error monitoring input (nERR_MCU) with fault injection option to monitor the lock-step signal of the attached MCU.
    In this implementation, the SPI bus is used for the communication between the PMIC and the MCU. This is done using the two pins for I2C (SCK, SDI) and GPIO2 and GPIO3 (CS0, SDO). When the SPI is configured instead of the two I2C interfaces, the SPI can access all of the registers, including the Q&A Watchdog registers.
  • Voltage Monitors (VMON): The voltage monitoring pins within the LP876242-Q1 have been connected to the 1V2_FILTERED and 5V rails. In the event of an under voltage or over voltage event, this allows the PMIC to monitor these rails and using SOC_nRESET_FROM_PMIC (GPIO10) issue a hard reset to the SOC. These inputs are low pass filtered to eliminate any short term events that would not adversely affect the operation of the system. The connection of these monitors is made directly at the connection to the radar. This avoids the situation where the ferrite bead in the power filters could fail and not be detected. The VMON thresholds and the actions taken during an OV/UV condition are configured in the Non-Volatile Memory (NVM) settings of the PMIC, and are re-configurable over SPI.
  • Additional Voltage Monitoring: To monitor the VIN_RF1 and VIN_RF2 rails, they are connected to ADC inputs on the SOC. If the rails monitored by the PMIC are functioning correctly, the SOC will be powered and the ADC will be able to monitor the RF rails. The action(s) taken by the SOC during a failure are configurable in software.
  • The watchdog monitors the correct operation of the MCU. This watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. When the watchdog detects an incorrect operation of the MCU, the LP876242-Q1 device pulls the SOC_nRESET_FROM_PMIC (GPIO10) pin low. This process triggers a restart of the SOC and FE1/FE2.