SBAA586 October   2023 AMC23C11 , UCC23513

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2System Challenge on Isolated Gate Drivers With Integrated DESAT
  6. 3System Approach With UCC23513 and AMC23C11
    1. 3.1 System Overview and Key Specification
    2. 3.2 Schematic Design
      1. 3.2.1 Circuit Schematic
      2. 3.2.2 Configure VCE(DESAT) Threshold and DESAT Bias Current
      3. 3.2.3 DESAT Blanking Time
      4. 3.2.4 DESAT Deglitch Filter
    3. 3.3 Reference PCB Layout
  7. 4Simulation and Test Results
    1. 4.1 Simulation Circuit and Results
      1. 4.1.1 Simulation Circuit
      2. 4.1.2 Simulation Results
    2. 4.2 Test Results With 3-Phase IGBT Inverter
      1. 4.2.1 Brake IGBT Test
      2. 4.2.2 Test Results on a 3-Phase Inverter With Phase to Phase Short
  8. 5Summary
  9. 6References
  10. 7Revision History

3.2.3 DESAT Blanking Time

The blanking time for DESAT monitoring, the tBLANK , is required to prevent false trig at the turn-on event of the IGBT. Capacitor C14 and resistors of R10 to R14 delay the VCE sensing signal to reach the isolated comparator's input VCIN. The delay is controlled by the charging time of C14 through the equivalent resistance REQ of the voltage divider R13 and R14:

Equation 6. REQ≈R13 // R14 =3 kΩ // 15 kΩ = 2.5 kΩ

Choose a C14 of 330 pF, then the time constant of the RC filter is:

Equation 7. Tau=REQ×C14=2.5 kΩ × 330 pF = 0.82 μs

The actual blanking time depends on the ratio of the configured VCE(DESAT) steady state threshold over the actual VCE(SAT) voltage of the IGBT in an over-current event, and can be approximated per Equation 8.

Equation 8. tBLANK=-ln⁡1-VCEDESATVCESAT×REQ×C14

Therefore, it is important to adjust the steady state VCE(DESAT) threshold and the blanking time constant according to the individual IGBT used in the system. Refer to below table for some values with the default settings of the VCE(DESAT) steady state threshold at 8 V:

Table 3-2 Effective Blanking Time With Default VCE(DESAT) Setting

IGBT VCE(SAT) [V]

≥ 14.5

12.5

11

10

9

8.5

tBLANK [μS]

0.7

0.9

1.1

1.4

1.9

2.4

CAUTION: Avoid to configure the steady state threshold VCE(DESAT) too close to the IGBT’s actual VCE(SAT) in an over-current condition, since the effective blanking time will be significantly larger than the configured blanking time constant.