SFFS081 March   2021 TLIN2029A-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TLIN2029A-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the device pin diagram. For a detailed description of the device pins, please refer to the Pin Configuration and Functions section in the TLIN2029A-Q1 data sheet.

GUID-49BF2935-5E11-43B6-A7EE-F7DEBA58FF9B-low.gif Figure 4-1 DRB Pin Diagram
GUID-DDB8253D-714A-41DF-8CF2-B5A993E20690-low.svg Figure 4-2 D Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • All conditions within the recommended operating conditions
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
RXD1RXD biased dominant, no communication from LIN bus to MCU possibleB
EN2Device may only operate in Standby Mode after power-on. If short occures in Normal mode, the part would be forced to enter sleep mode and could disable LIN communicationB
NC3No impact to performanceD
TXD4TXD biased dominant, no communication from MCU to LIN bus possibleB
GND5NoneD
LIN6LIN biased dominant, no LIN communication possibleB
VSUP7Device is unpowered and will not functionB
NC8No impact to performanceB
Note: DRB package includes a thermal pad
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
RXD1No communication from LIN bus to MCU possibleB
EN2Biased low due to internal pull-down so device in standby modeB
NC3No impact to performanceD
TXD4No communication from MCU to LIN bus possibleB
GND5Device is unpowered and will not functionB
LIN6No LIN communication possibleB
VSUP7Device is unpowered and will not functionB
NC8No impact to performanceD
Note: DRB package includes a thermal pad
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure Effect(s)Failure Effect Class
RXD1ENDevice will go into sleep mode when a dominant bit is received on the LIN bus, disabling communicationB
EN2NCNo impact to performanceD
NC3TXDNo impact to performanceD
GND5LINLIN biased dominant, no LIN communication possibleB
LIN6VSUPLIN biased recessive, no LIN communication possibleB
VSUP7NCNo impact to performanceD
Note: The DRB package includes a thermal pad. There is a chance the thermal pad is soldered down and could short to any pin on device. What the thermal pad is soldered to determines the behavior. Example: if soldered to a ground plane then the adjacent pins would behave as if shorted to ground.
Table 4-5 Pin FMA for Device Pins Short-Circuited to VSUP supply
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
RXD1Absolute maximum voltage violation, transceiver may be damagedA
EN2Absolute maximum voltage violation, transceiver may be damagedA
NC3No impact to performanceD
TXD4Absolute maximum voltage violation, transceiver may be damagedA
GND5Device is unpowered and will not functionB
LIN6LIN biased recessive, no LIN communication possibleB
VSUP7NoneD
NC8No impact to performanceD
Note: DRB package includes a thermal pad