SFFS148A november   2022  – june 2023 TPSI2140-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
  7. 5Revision History

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPSI2140-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-4 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1. Note that when pin short to ground case is discussed, only primary side ground shorts are considered.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Below is the TPSI2140-Q1 pin diagram package. For a detailed description of the device pins, see the Pin Configuration and Functions section in the TPSI2140-Q1 data sheet.

GUID-20210115-CA0I-BZ82-RSQT-CPQQPLKNWBGC-low.svg Figure 4-1 TPSI2140-Q1 Pin Diagram
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
VDD 1 Device in OFF state (UVLO), secondary side switch in OFF state B
GND 2 No effect D
EN 3 Device in OFF State, secondary side switch in OFF state B
NC/GND 4 No effect D
NC/GND 5 No effect D
NC/GND 6 No effect D
NC/GND 7 No effect D
GND 8 No effect D
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
VDD 1 Device in OFF state (UVLO), secondary side switch in OFF state B
GND 2 No effect D
EN 3 Device in OFF State, secondary side switch in OFF state B
NC/GND 4 No effect D
NC/GND 5 No effect D
NC/GND 6 No effect D
NC/GND 7 No effect D
GND 8 No effect D
S2 9 No effect D
SM 10 No effect D
S1 11 No effect D
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Pin No. Description of Potential Failure Effect(s) Failure Effect Class
VDD 1 2 Device in OFF state (UVLO), secondary side switch in OFF state B
GND 2 3 Device in OFF State, secondary side switch in OFF state B
EN 3 4 No effect if pin 4 is NC, if pin 4 is GND the device will be in OFF state, secondary side switch in OFF state D or B
NC/GND 4 5 No effect D
NC/GND 5 6 No effect D
NC/GND 6 7 No effect D
NC/GND 7 8 No effect D
S2 9 10 Secondary side switch standoff voltage is halved. C
SM 10 11 Secondary side switch standoff voltage is halved. C