SFFS309A April   2022  – May 2022 TPS3704 , TPS3704-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Hardware Component Failure Modes Effects and Diagnostics Analysis (FMEDA)
    1. 2.1 Random Fault Estimation
      1. 2.1.1 Fault Rate Estimation Theory for Packaging
      2. 2.1.2 Fault Estimation Theory for Silicon Permanent Faults
      3. 2.1.3 Fault Estimation Theory for Silicon Transient Faults
      4. 2.1.4 The Classification of Failure Categories and Calculation
    2. 2.2 Using the FMEDA Spreadsheet Tool
      1. 2.2.1 Mission Profile Tailoring Tab
        1. 2.2.1.1 Confidence Level
        2. 2.2.1.2 Geographical Location
        3. 2.2.1.3 Life Cycle
        4. 2.2.1.4 Use Case Thermal Management Control (Theta-Ja) and Use Case Power
        5. 2.2.1.5 Safe vs Non-Safe (Safe Fail Fraction) for Each Component Type
        6. 2.2.1.6 Analog FIT Distribution Method
        7. 2.2.1.7 Operational Profile
      2. 2.2.2 Pin Level Tailoring Tab
      3. 2.2.3 Function and Diag Tailoring Tab
      4. 2.2.4 Diagnostic Coverage Tab
      5. 2.2.5 Customer Defined Diagnostics Tab
      6. 2.2.6 Totals - ISO26262 Tab
      7. 2.2.7 Details - ISO26262 Tab
      8. 2.2.8 Totals - IEC61508 Tab
      9. 2.2.9 Details - IEC61508 Tab
    3. 2.3 Example Calculation of Metrics
      1. 2.3.1 Assumptions of Use for Calculation of Safety Metrics
      2. 2.3.2 Summary of ISO 26262 Safety Metrics at Device Level
      3. 2.3.3 Summary of IEC 61508 Safety Metrics at Device Level
  4. 3Revision History

2.2.8 Totals - IEC61508 Tab

This tab is informational only. There are no selections the user can make in this tab.

The 'Totals - IEC61508' tab contains the results of the chip level FMEDA metrics based on the selections in the previous tabs. This tab summarizes the metrics as described by the IEC 61508 functional safety standard. The top table breaks out the overall FIT and diagnostic coverage for permanent faults of the die, transient faults of the die, package faults, and finally the overall sum of faults for each row. The following information is provided:

  • Total FIT (Raw FIT): The total base failure rate of the device using the described base FIT model under the environmental conditions input in the 'Mission Profile Tailoring' tab.
  • Safety related FIT: A subset of the total FIT that includes only the design blocks or device pins that are indicated as safety related on the 'Pin Level Tailoring' and 'Function and Diag Tailoring' tabs.
  • Probability of Hardware Failures - PFH (in FIT): The average frequency of a dangerous failure (only this device's contribution) to the assumed Electrical/Electronic/Programmable Electronic (E/E/PE) safety related system to perform the specified safety function over a given period of time. The selection of diagnostics in the 'Pin Level Tailoring' and 'Function and Diag Tailoring' tabs directly impact this number.
  • Safe Failure Fraction - SFF: The ratio of the average failure rates of safe plus dangerous detected failures and safe plus dangerous failures. The selection of diagnostics in the 'Pin Level Tailoring' and 'Function and Diag Tailoring' tabs directly impact this percentage.

There are also some intermediate calculations based on the terms in the IEC 61508 standard:

  • Total faults (λ): Same as the total FIT from above.
  • Total non safety related faults (λnSR)
  • Total safe faults (λs)
  • Total dangerous faults (λD)
  • Total dangerous detected faults (λDD)
  • Total dangerous undetected faults (λDU)