SFFS799 March   2024 TLV365-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 SOT-23 Package
    2. 2.2 SOIC Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 SOT-23 Package
    2. 4.2 SOIC Package

4.2 SOIC Package

Figure 4-2 shows the TLVx365-Q1 pin diagram for the SOIC package. For a detailed description of the device pins, see the Pin Configuration and Functions section in the TLVx365-Q1 data sheet.

GUID-8227EF26-4791-4DBC-91C8-7DAF070800F5-low.gif Figure 4-2 Pin Diagram (SOIC Package)
Table 4-6 Pin FMA for Device Pins Short-Circuited to Ground
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
VOUTA 1 Short to GND may cause device to overheat. B
-IN A 2 Input at V- (GND) is valid input, however, desired application result is unlikely. C
+IN A 3 Input at V- (GND) is valid input, however, desired application result is unlikely. C
V- 4 Normal operation, unless dual supply voltage was intended. D
+IN B 5 Input at V- (GND) is valid input, however, desired application result is unlikely. C
-IN B 6 Input at V- (GND) is valid input, however, desired application result is unlikely. C
VOUTB 7 Short to GND may cause device to overheat. B
V+ 8 Diodes from input to V+ may turn on due to input signal and cause electrical overstress (EOS). A
Table 4-7 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
VOUTA 1 Output can be left open. There is no effect on the device, but the output will not be measured. C
-IN A 2 Floating input, circuit will likely not function as expected. C
+IN

A

 3 Floating input, circuit will likely not function as expected. C
V- 4 Lowest voltage pin will try to power the V- pin of the device. B
+IN B 5 Floating input, circuit will likely not function as expected. C
-IN B 6 Floating input, circuit will likely not function as expected. C
VOUTB 7 Output can be left open. There is no effect on the IC, but the output will not be measured. C
V+ 8 Highest voltage output pin will try to power the

V+ pin of the device.

 B
Table 4-8 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effect(s) Failure Effect Class
VOUTA 1 -IN A Channel 1 configured in unity gain C
-IN A 2 +IN A No damage to device. Application circuit will not work. C
+IN A 3 V- Input at V- (GND) is valid input, however, desired application result is unlikely. C
V- 4 +IN B Input at V- (GND) is valid input, however, desired application result is unlikely. Pins are not adjacent to each other. C
+IN B 5 -IN B No damage to device. Application circuit will not work C
-IN B 6 VOUTB Channel 2 configured in unity gain C
VOUTB 7 V+ Short to V+ may cause device to overheat. B
V+ 8 VOUTA Short to V+ may cause device to overheat. Pins are not adjacent to each other. B
Table 4-9 Pin FMA for Device Pins Short-Circuited to V+
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
VOUTA 1 Short to VS+ may cause device to overheat. B
-IN A 2 Input at V+ is valid input, however, desired application result is unlikely. C
+IN A 3 Input at V+ is a valid input, however, desired application result is unlikely. C
V- 4 Diodes from input to V- may turn on due to input signal and cause electrical overstress (EOS). A
+IN B 5 Input at V+ is a valid input, however, desired application result is unlikely. C
-IN B 6 Input at V+ is a valid input, however, desired application result is unlikely. C
VOUTB 7 Short to VS+ may cause device to overheat. B
V+ 8 Normal Operation. D