SLAAE59 may 2023 AFE539A4

Design Goals
Design Description
Design Notes
Testing Results
1. Measured Design Characteristics
Register Settings
Pseudo Code Example
Design Featured Devices
Design References

Design Notes

Device Selection

The AFE539A4 is capable of controlling DC/DC converters: for this reference design the TPS63070 buck-boost converter is selected. The TPS63070 has an input voltage range of 2 V to 16 V and an output range of 2.5 V to 9 V with the ability to drive up to 2 A of current.

General Overview

The AFE539A4 Smart Analog Front End (AFE) With Quad-Channel, 10-Bit DAC and ADC for Proportional-Integral (PI) Control With I2C and SPI data sheet recommends using a 100-nF decoupling capacitor for the VDD pin, and a 1.5 µF or greater bypass capacitor for the CAP pin. The CAP pin is connected to the internal low-dropout (LDO) linear regulator. Place these capacitors close to the device pins.

Due to the bidirectional current flow in a TEC module, a diode can be connected between the TPS VIN pin and the supply to protect the supply from any back-current flow. TEC Control DC/DC Protection Diode Diagram shows the flow of current with the red arrows representing the current flow from the supply, and the blue arrows representing the reverse current which can be harmful to the supply. This diode can be ignored if current sinking to the source is not a concern.

Diodes exhibit a turn-on voltage that needs to be accounted for. The voltage supply must be offset by the diode turn-on voltage, which in the case of this design is 500 mV. Conversely, the nominal output of the TPS63070 can be set to 4.5 V instead of raising the supply voltage. Regardless of which voltage is offset, track any changes that can affect the calculations of the biasing resistor network (R1, R2, R3). The diode is bypassed in this design and the 500-mV offset is ignored for resistors calculations.

TEC Control DC/DC Protection Diode Diagram

The comparator input (pin FB2) on the AFE539A4 can be used along with a current-sense amplifier for overcurrent detection. Connect the comparator input to VDD or to GND when the comparator is not in use. This design does not use the comparator and the input is connected to VDD. Register SRAM-DATA-36 sets the comparator threshold and SRAM-DATA-39 sets the safe output setting.

The pin FB2 on the TPS63070 is used for scaling the voltage output. Typically, this pin has a resistor connected between pins FB2 and FB on the TPS63070 to change the voltage-divider ratio on the FB pin to control the output voltage. The FB2 pin is not used for this configuration and is grounded. The TPS63070 PG pin is an open-drain, power-good output. A 100-kΩ resistor is recommended for the PG pin.

Nominal Value Selection

The voltage across the TEC is bipolar, where the polarities are used to describe the direction of the current flow. The VOUT pin of the DC/DC converter is set to operate in the range of 2.5 V to 7.5 V, where 2.5 V yields negative voltage across TEC and 7.5 V yields positive voltage.

The positive voltage of the TPS63070 is calculated by the difference between the VOUT maximum (7.5 V) and the input voltage, VIN (5 V). Similarly, the negative voltage is calculated by the difference between the minimum VOUT (2.5 V) and VIN. These voltage values are selected to create a 500-mA current with the resistive TEC element.

Resistor Network Design

The resistive network is designed to set a margin on the VOUT pin of the DC/DC converter to three different desired output voltages.

Case 1: VDAC = 0, VOUT is set to output maximum voltage (VHIGH), which is 7.5 V
Case 2: VDAC = 800 mV = VNOMINAL, VOUT is set to 5 V
Case 3: VDAC is set to maximum value, VOUT is set to minimum voltage ( VMIN ), which is 2.5 V

Using a nominal current of 5 µA, the following equations are used to determine the resistor values to produce the respective voltage output. Set the nominal current for the resistor to be significantly larger than the 100-nA leakage current on the FB pin of the TPS63070.

R_{1} = \frac{V_{N O M I N A L} - V_{F B}}{I_{N O M I N A L}} = 840 k Ω

R_{2} = \frac{R_{1} \times V_{F B}}{V_{N O M I N A L} - V_{F B}} = 160 k Ω

R 3 = \frac{V_{F B} - V_{D A C}}{I_{R 1}}

To calculate the value for R3, the current through R1 must first be obtained. This equation demonstrates how to calculate the current through R1 using Case 1, where VDAC = 0 V and VOUT = 7.5 V.

I_{R 1} = \frac{V_{O U T} - V_{F B}}{R 1} = \frac{6.7 V}{840 k Ω} = 7.98 µ A .

The following figure illustrates the flow of current across resistors R1 and R2, as well as the flow of current towards the DAC.

TEC Control DC/DC Resistor Divider Calculation Using Case 1

The current through R1 is the total current between the branches of R2 and R3, which is calculated using Ohm's law. For this case, the DAC has a 0-V output.

R 3 = \frac{V_{F B} - V_{D A C}}{I_{R 1}} = \frac{0.8 V - 0 V}{2.98 µ A} = 268.8 k Ω .

The 5-V nominal voltage of the TPS63070 is the same as VIN, so there is zero current through the TEC. With no voltage drop, there is no temperature change in the TEC due to the lack of current. The following resistor values are derived with a nominal voltage of 5 V, nominal current of 5 µA, and a feedback voltage of 800 mV.

R_{1} = \frac{5 V - 0.8 V}{5 µ A} = 840 k Ω

R_{2} = \frac{840 k Ω \times 0.8 V}{5 V - 0.8 V} = 160 k Ω

With a VOUT of 2.5 V on the TPS63070, the VMIN case, the voltage output of the DAC on the AFE539A4 is calculated based on the V_min of 5.2 V and the calculated resistor value R3.

I_{1} = \frac{2.5 V - 0.8 V}{840 k Ω} = 2.02 µ A

The DAC VOUT is then calculated using the following equation.

V_{D A C} = 0.8 V + (2.98 µ A \times 268.8 k Ω) = 1.6 V

TEC Control DC/DC Resistor Divider Calculation Using VMIN Case

Selecting the Thermistor Value

A negative temperature coefficient (NTC) thermistor increases in resistance as temperature decreases. The data sheet for the thermistor defines the temperature versus resistance relationship. A voltage divider is created with the R_DIV resistor to get a voltage output from the NTC. Selecting the right R_DIV value determines the input voltage range (and therefore the temperature). Using a 12-kΩ resistor provides the ADC input with a voltage that is within the range of –25°C to 100°C. With the resistor divider, this temperature range is equivalent to the range of 0 to 5 V. This voltage divider can be calculated with the 5-V VDD and 10-kΩ thermistor used in this circuit. Using the equation for a voltage divider, the resistor divider value is calculated with the ADC input range of 0 V to 5 V over the given temperature range.

Relation of Component Temperatures to R_NTC Resistor Values

Component Temperature	R_NTC Resistance
–25°C	105 kΩ
25°C	10 kΩ
100°C	700 Ω

Table 1-1 Relation of Component Temperatures to V_OUT Outputs

Component Temperature	VOUT
–25°C	0.512 V
25°C	2.72 V
100°C	4.72 V

An additional 1-nF capacitor, parallel to R_DIV, is used for filtering noise. The following figure shows R_DIV and R_NTC in relation to the TEC.

TEC Control DC/DC Decoupling Capacitor Placement

PI Controller Setup

The AFE539A4 has an internal state machine that is factory-programmed to function as a proportional integral (PI controller). The two main components of a PI controller are the proportional and integral gains. The proportional gain (KP) is multiplied with the instantaneous error. The higher the KP value, the faster the loop corrects, but the loop is more prone to higher overshoot and can take longer to settle. The integral gain (KI) is multiplied to the accumulated error. KI can lower the steady state error but can lead to larger oscillations if too small of a value is used. The proportional and integral gains are programmed in the 16-bit registers. SRAM-DATA-35 is the register for proportional gain. SRAM-DATA-38 is the register for integral gain. The KP and KI selected for this system are: KP = 2048 and KI = 15. These gains are derived by iteratively testing the KP and KI values based on a response from the TEC component to maintain a speedy response that minimizes any ripple on the temperature of the TEC.

In addition to configuring the PI gains, the setpoint value (SRAM-DATA-37) must be configured. The PI controller compares the setpoint with the ADC input. With a setpoint value of 0x02DA, the AFE539A4 adjusts VDAC until the ADC input of 3.46 V or 40°C is achieved. The following equation shows how a value of 3.46 V is obtained for the setpoint value.

V_{S E T P O I N T} = V D D \times \frac{R_{D I V}}{R_{N T C} + R_{D I V}} = 5 \times \frac{12 k Ω}{12 k Ω + 5356 k Ω} = 3.46 V

The value of 5.356 kΩ in the preceding equation is based on the temperature to resistance conversion from the data sheet of the NTC thermistor at 40°C.

The polarity of the loop is configurable. For this reference design, the loop polarity is left at the default (0 in SRAM-DATA-39). Additionally, the ADC mode can be configured in this register. The ADC0-MODE bit determines the impedance of the ADC. If the bit is low, the ADC on the AFE539A4 has an infinite impedance, resulting in the ADC_Code equation calculation using a K value of 3. If the bit is low, the impedance is finite and the K value is 1. For this design, the ADC0 has a finite impedance and the safe output is used. In failure scenarios, safe output can be used as a backup to test device functionality.

Register SRAM-DATA-36 configures the threshold of comparator 2. A comparator threshold of 0x8000 is used for this design.

ADC and DAC Code Calculations

Both the ADCs and the DACs on the AFE539A4 are 10 bits. The DAC and ADC code are calculated using the following equations.

{D A C}_{C o d e} = \frac{V_{D A C}}{V_{R E F} \times G A I N} {\times 2}^{N}

A D C_{C o d e} = \frac{V_{I N} \times K}{V_{F S}} \times 2^{N} - 1

N is the total number of bits. This design configures the DAC VOUT channel to use the internal 1.21 V reference with a gain of 1.5 ×, and the ADC input to use the internal 1.21-V reference with a gain of 4 ×. The K value for the ADC is an attenuation factor and has a value of 1 to set the ADC to infinite impedance.

To calculate the ADC setpoint, use the following equation.

A D C_{S E T P O I N T} = \frac{V_{I N} \times K}{V_{F S}} \times 2^{N} - 1 = \frac{4.72 \times 1}{1.21 \times 4} \times 1023 = 997

Setting the ADC common-mode value is also important for achieving fluid control of the PI controller.

The system uses 0.8 V as a threshold value to reach the programmed setpoint for the controller when the setpoint (SRAM-DATA-34) for the DAC code is set to 0.8 V. Using the DAC range of 0 V to 1.6 V, the following decimal values are derived for the minimum (SRAM-DATA-33) and maximum (SRAM-DATA-32) DAC values for this design:

{D A C}_{M A X} C o d e = \frac{1.6 V}{1.21 \times 1.5} \times 2^{10} = 903 d

{D A C}_{M I N} C o d e = \frac{0.8 V}{1.21 \times 1.5} \times 2^{10} = 451 d

Note: The common mode value selected is the same value as the DAC minimum code.