SLAAE72 December   2022 MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
  4. 2Low-Power Features in PMCU
    1. 2.1 Overview
      1. 2.1.1 Power Domains and Power Modes
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Supply Supervisors
      2. 2.2.2 Peripheral Power Control
      3. 2.2.3 VBOOST for Analog Muxes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
      2. 2.3.2 Clocks
      3. 2.3.3 Asynchronous Fast Clock Requests
      4. 2.3.4 Shutdown Mode Handling
  5. 3Low-Power Optimization
    1. 3.1 Low-Power Basics
    2. 3.2 MSPM0 Low-Power Feature Use
      1. 3.2.1 Low-Power Modes
      2. 3.2.2 System Clock and Peripheral Operation Frequency
      3. 3.2.3 I/O Configuration
      4. 3.2.4 Event Manager
      5. 3.2.5 Analog Peripheral Low-Power Features
      6. 3.2.6 Run Code From RAM
    3. 3.3 Software Coding Strategies
    4. 3.4 Hardware Design Strategies
  6. 4Power Consumption Measurement and Evaluation
    1. 4.1 Current Evaluation
    2. 4.2 Current Measurement
      1. 4.2.1 Current Measurement

1 Overview

TI’s scalable MSPM0Lxx MCUs are based on Arm® Cortex®-M0+ core, with a maximum CPU speed of 32 MHz, which provides the basic general-purpose functions with low-power features. The MCUs are available with up to 256KB of on-chip flash and up to 32KB on-chip SRAM with extended scalable analog Integration. They also integrate an efficient power supply architecture and various power modes that helps the power consumption reduction and simplify application design. Its overall low-power performance is show in Table 1-1. For more details, refer to the device-specific data sheet.

Table 1-1 MSPM0Lxx Series Low-Power Performance
Low-Power Mode MSPM0Lxx
Run(1)(5) 85 µA/MHz
Sleep(2)(5) 200 μA at 4 MHz
Stop(3)(5) 50 μA at 32 kHz
Standby(4)(5) 1.1 µA
Shutdown(5) 50 nA with IO wakeup capability
(1) MCLK = SYSOSC = 32 MHz, CoreMark, execute from flash
(2) MCLK = SYSOSC, CPU is halted
(3) SYSOSC off, DISABLESTOP = 1, ULPCLK = LFCLK, SRAM and flash are in retention
(4) STOPCLKSTBY = 1, TIMG0 enabled
(5) Typical value at 25°C and VDD = 3.3 V. All inputs tied to 0 V or VDD. Outputs do not source or sink any current. All peripherals are disabled.

This application note was created to build a simple framework to help developers understand the MSPM0Lxx series low-power features, how power can be optimized to meet the specific needs based on MSPM0, and how to evaluate and measure it. Figure 1-1 shows the design flow for a low-power design.

Figure 1-1 Low-Power Development Process

Table 1-2 lists the items to check during development.

Table 1-2 Low-Power Development Checklist
Number Classification Item Comment
1 Hardware design MCU power supply Reduce MCU power supply no lower than 1.62 V.
2 Resistors Choose large resistors after meeting system requirement.
3 Capacitors Choose low leakage capacitors.
4 Power IC Normally choose a linear regulator.
5 Software coding Conditional code execution Use a conditional wake-up and code execution structure.
6 Nonblocking programming Avoid blocking mode by using while loop.
7 Optimize code size Choose TI Arm Clang, Fully use compiler features and write code with good coding style.
8 MSPM0 low-power feature usage Use low-power modes Use different power modes (RUN, SLEEP, STOP, STANDBY, and SHUTDOWN) and three lower mode policy options (XX0, XX1, XX2) according to the application requirement.
9 Reduce system clock and peripheral operation frequency Only use the needed system clock frequency. Reduce peripherals operation frequency and turn them off when not used.
10 I/O configuration Leave the unused pin as default high-Z configuration. Reduce the use of internal pull-up or pull-down resistors. Pay attention to the IO-latch in low-power modes.
11 Use event manager Use event manager to realize peripherals trigger DMA or peripherals trigger peripherals to reduce the CPU usage.
12 Use analog peripherals’ low-power features Compromise between performance and low-power consumption for the ADC, COMP, OPA and GPAMP.
13 Run code from RAM Move a part of common used code from flash to RAM.