SLAAEF9 November 2023 MSPM0L1306
MSPM0 and RL78 both support serial peripheral interface (SPI). For the RL78's SPI, SPI function is in the SAU (Serial Array Unit) peripherals used as CSI (Clocked Serial Interface). Besides, MSPM0 uses Controller and Peripheral to represent the communication parties of the SPI. Overall, MSPM0 and RL78 SPI support is comparable with the difference listed in Table 4-3.
Feature | RL78 | MSPM0 |
---|---|---|
Operation wires | SCK, SI, SO | SCLK, PICO, POCI, CSx |
Controller or peripheral operation | Yes | Yes |
Data bit width (controller mode) | 7 to 16 bit (1) | 4 to 16 bit |
Data bit width (peripheral mode) | 7 to 16 bit | |
Maximum speed | 16 MHz (CSI00 only, Controller) 8 MHz (Else, Controller) 5.33 MHz (Else, Peripheral) |
MSPM0L: 16 MHz |
MSPM0G: 32 MHz | ||
Simplex transfers (unidirectional data line) | Yes | Yes |
Hardware chip select management | No | Yes (4 peripherals) |
Phase control of I/O clock | Yes | Yes |
Transfer direction setting with MSB-first or LSB-first shifting | Yes | Yes |
SPI format support | Motorola | Motorola, TI, MICROWIRE |
Hardware CRC | No | No, MSPM0 offers SPI parity mode |
TX FIFO depth | No | 4 |
RX FIFO depth | No | 4 |
SPI Code Examples
Information about SPI code examples can be found in the MSPM0 SDK examples guide.