SLAAEK4 January   2024 MSPM0C1104

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Comparison Between TIMA and TIMG
  6. 3 Use Case - 3 Pairs of Complementary PWM with Deadband Insertion
    1. 3.1 Principle
    2. 3.2 Implement
  7. 4 Use Case - Timing-Critical PWM Control with Shadow Load and Compare
    1. 4.1 Principle
    2. 4.2 Implement
  8. 5 Use Case - Fault Handler
    1. 5.1 Principle
    2. 5.2 Implement
  9. 6 Use Case – PWM Disable with Software Force Output
    1. 6.1 Principle
    2. 6.2 Implement
  10. 7 Use Case - Asymmetric PWM
    1. 7.1 Principle
    2. 7.2 Implement
  11. 8 Use Case – Optimal Interrupt Generation with Repeat Counter
    1. 8.1 Principle
    2. 8.2 Implement
  12. 9 Summary
  13. 10References

8.2 Implement

When the timer counter is advancing, the repeat counter advances once the counter reloads. The user can set the how many timer counter reloads occur until generating the interrupts and events. Once repeat counter equals the setting number, the repeat counter is reset back to zero and a Repeat Counter Zero event occurs (REPC) in the Interrupt and Event Status registers.

Additionally, the repeat counter provides the ability to suppress generation of Zero, Load, and Compare events when TIMA.RC does not equal zero. Based on this, MCU can avoid generating excessive and unnecessary interrupts.

As shown in Figure 8-9, the timer counter is configured for down-counting mode and zero events are generated once timer counter = 0. Repeat counter is used to suppress zero and load events until 4 timer reloads occur. The user can configure repeat counter to generate Optimal Interrupt as needed.

GUID-D1F3B624-CEEC-42E9-B36D-8398B5AED963-low.svg Figure 8-1 Event Suppressed by Repeat Counter

To accelerate development, please refer to the following resources.