SLAU929 April   2024 MSPM0C1104 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0L1105 , MSPM0L1304 , MSPM0L1305 , MSPM0L1306

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of Microchip AVR ATmega and ATiny MCUs to MSPM0
  5. 2Ecosystem and Migration
    1. 2.1 Software Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 MPLAB X IDE vs Code Composer Studio IDE (CCS)
      3. 2.1.3 MPLAB Code Configurator vs SysConfig
    2. 2.2 Hardware Ecosystem
    3. 2.3 Debug Tools
    4. 2.4 Migration Process
    5. 2.5 Migration and Porting Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
        1. 3.2.2.1 Memory Banks
        2. 3.2.2.2 Flash Memory Regions
        3. 3.2.2.3 NONMAIN Memory
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Power Modes
      3. 3.5.3 Entering Lower-Power Modes
    6. 3.6 Interrupt and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
      2. 3.6.2 Event Handler and EXTI (Extended Interrupt and Event Controller)
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Bootstrap Loader (BSL) Programming Options
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 I2C
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  9. 6References

3.3 Power Up and Reset Summary and Comparison

Similar to Microchip 32 bit devices, MSPM0 devices have a minimum operating voltage and have modules in place to make sure that the device starts up properly by holding the device or portions of the device in a reset state. Table 3-4 shows a comparison on how this is done between the two families and what modules control the power up process and reset across the families.

Table 3-4 Comparison of Power up
ATmega ATtiny MSPM0 Devices
Modules governing power up and resets Power Manager module, System Controller and Reset Module Brown out detector, Reset Controller Module governing power up and resets PMCU (Power Management and Clock Unit)
Voltage-Level Based Resets
POR (Power-On Reset) Complete device reset. First level voltage release for power up. Lowest voltage level for power down. POR (Power-On Reset) Complete device reset. First level voltage release for power up. Lowest voltage level for power down.
BOR (Brownout Reset) with configurable levels Programmable Threshold for triggering resets or interrupts Configurable BOR (Brownout Reset) Can be configured as a reset or interrupt, with different voltage thresholds.

Microchip defines different reset types, while MSPM0 devices have different levels of reset states. For MSPM0 devices, the reset levels have a set order, and when a level is triggered, all subsequent levels are reset until the device is released into RUN mode. Table 3-5 shows the reset types in Microchip 8-bit AVR MCUs Devices. Table 3-6 gives a brief description of MSPM0 reset states. Figure 3-1 shows the relationship between all of the MSPM0 reset states.

Table 3-5 Reset Type in ATmega and ATtiny devices
ATmega and ATtiny Reset Types
Reset Source Power Supply Reset User Reset
Reset Name Power on reset, brown out detect reset External Reset WDT Reset, software reset, Unified program and debug interface reset
Table 3-6 Comparison of Reset Domains
MSPM0 Reset States(1)
POR Typical triggers: POR voltage levels, SW trigger, NRST held low for >1s. Resets shutdown memory, re-enables NRST and SWD, triggers BOR
BOR Typical triggers: POR or BOR voltage level, exit from shutdown mode. Resets PMU, VCORE, and associated logic. Triggers BOOTRST.
Boot reset (BOOTRST) Typical triggers: BOR or software trigger, fatal clock failure, NRST held low for <1 s. Executes boot configuration routine. Resets majority of core logic and registers, including RTC, clock, and IO configurations.(2) SRAM power cycled and lost. Triggers SYSRST.
System reset (SYSRST) Typical triggers: BOOTRST, BSL entry or exit, watchdog timer, software trigger, debug subsystem. Resets CPU state and all peripherals except RTC, LFCLK, LFXT, and SYSOSC frequency correction loop. Device enters RUN mode on exit.
CPU-only reset (CPURST) Software and debug subsystem triggers only. Resets CPU logic only. Peripheral state are not affected.
RTC and associated clocks are reset through BOOTRST, BOR, or POR.(2)
(1) Not all reset triggers described. Refer to the PMCU chapter of the device TRM for all available reset triggers.
(2) If BOOTRST cause was through NRST or software trigger, RTC, LFCLK, and LFXT/LFLCK_IN configurations and IOMUX settings are NOT reset to allow RTC to maintain operation through external reset.
GUID-470C42B3-F7CD-49FD-9FA4-7BA4B48CD360-low.svg Figure 3-1 MSPM0 Reset Levels