SLAZ271AB October   2012  – May 2021 MSP430F5327

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PN80
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC25
    2. 6.2  ADC27
    3. 6.3  ADC29
    4. 6.4  ADC42
    5. 6.5  ADC69
    6. 6.6  BSL6
    7. 6.7  BSL7
    8. 6.8  COMP10
    9. 6.9  CPU21
    10. 6.10 CPU22
    11. 6.11 CPU23
    12. 6.12 CPU26
    13. 6.13 CPU27
    14. 6.14 CPU28
    15. 6.15 CPU29
    16. 6.16 CPU30
    17. 6.17 CPU31
    18. 6.18 CPU32
    19. 6.19 CPU33
    20. 6.20 CPU34
    21. 6.21 CPU35
    22. 6.22 CPU37
    23. 6.23 CPU39
    24. 6.24 CPU40
    25. 6.25 CPU47
    26. 6.26 DMA4
    27. 6.27 DMA7
    28. 6.28 DMA8
    29. 6.29 DMA10
    30. 6.30 EEM9
    31. 6.31 EEM11
    32. 6.32 EEM13
    33. 6.33 EEM14
    34. 6.34 EEM15
    35. 6.35 EEM16
    36. 6.36 EEM17
    37. 6.37 EEM19
    38. 6.38 EEM21
    39. 6.39 EEM23
    40. 6.40 FLASH33
    41. 6.41 FLASH34
    42. 6.42 FLASH35
    43. 6.43 FLASH37
    44. 6.44 JTAG20
    45. 6.45 JTAG26
    46. 6.46 JTAG27
    47. 6.47 LDO1
    48. 6.48 MPY1
    49. 6.49 PMAP1
    50. 6.50 PMM9
    51. 6.51 PMM10
    52. 6.52 PMM11
    53. 6.53 PMM12
    54. 6.54 PMM14
    55. 6.55 PMM15
    56. 6.56 PMM17
    57. 6.57 PMM18
    58. 6.58 PMM20
    59. 6.59 PORT15
    60. 6.60 PORT16
    61. 6.61 PORT19
    62. 6.62 PORT24
    63. 6.63 RTC3
    64. 6.64 RTC6
    65. 6.65 SYS10
    66. 6.66 SYS12
    67. 6.67 SYS14
    68. 6.68 SYS16
    69. 6.69 TAB23
    70. 6.70 USCI26
    71. 6.71 USCI30
    72. 6.72 USCI31
    73. 6.73 USCI34
    74. 6.74 USCI35
    75. 6.75 USCI39
    76. 6.76 USCI40
    77. 6.77 WDG4
  7. 7Revision History

FLASH37

FLASH Module

Category

Functional

Function

Corrupted flash read when SVM low-side flag is triggered

Description

If the SVM low side is enabled, a change in the VCORE voltage level (an increase in the VCORE level) may cause the currently executed read operation from flash to be incorrect and may lead to unexpected code execution or incorrect data. This can happen under any one of the following conditions:

- When the VCORE is changed in application, the SVM low side is used to indicate if the core voltage has settled by using the SVMDLYIFG flag. The failure occurs only when a flash access is concurrent to the expiration of the settling time delay.

- Unexpected changes in the VCORE voltage level

For code examples and detailed guidance on the PMM operation and software APIs for PMM configuration see the driverlib APIs from 430Ware (MSP430Ware).

Workaround

- Execute the procedure to change the VCORE level from RAM.

or

- If executing from flash, follow the procedure below when increasing the VCORE level. Note: To apply this workaround, the SVM low-side comparator must operate in normal mode (SVMLFP = 0 in SVMLCTL).

// Set SVM highside to new level and check if a VCore increase is possible
  SVSMHCTL = SVMHE | SVSHE | (SVSMHRRL0 * level);
  // Wait until SVM highside is settled
  while ((PMMIFG & SVSMHDLYIFG) == 0);
  // Clear flag
  PMMIFG &= ~SVSMHDLYIFG;

  // Set also SVS highside to new level
  // Vcc is high enough for a Vcore increase
  SVSMHCTL |= (SVSHRVL0 * level);
  // Wait until SVM highside is settled
  while ((PMMIFG & SVSMHDLYIFG) == 0);
  // Clear flag
  PMMIFG &= ~SVSMHDLYIFG;
  
//**************flow change for errata workaround ************
  // Set VCore to new level
  PMMCTL0_L = PMMCOREV0 * level;


  // Set SVM, SVS low side to new level
  SVSMLCTL = SVMLE | (SVSMLRRL0 * level)| SVSLE | (SVSLRVL0 * level);
  // Wait until SVM, SVS low side is settled
  while ((PMMIFG & SVSMLDLYIFG) == 0);
  // Clear flag
  PMMIFG &= ~SVSMLDLYIFG;

//**************flow change for errata workaround ************