SLAZ495AB December   2012  – September 2021 MSP430F5359

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
    1.     6
    2.     7
      1.      8
      2.      9
    3.     10
  6.   11
    1.     12
    2.     13
    3.     14
    4.     15
    5.     16
    6.     17
    7.     18
    8.     19
    9.     20
    10.     21
    11.     22
    12.     23
    13.     24
    14.     25
    15.     26
    16.     27
    17.     28
    18.     29
    19.     30
    20.     31
    21.     32
    22.     33
    23.     34
    24.     35
    25.     36
    26.     37
    27.     38
    28.     39
    29.     40
    30.     41
    31.     42
    32.     43
    33.     44
    34.     45
    35.     46
    36.     47
    37.     48
    38.     49
    39.     50
  7.   51

PORT26

PORT Module

Category

Functional

Function

Incorrect values for P1.1 / P1.2 input pins during power-up

Description

If P1.1/P1.2 is pulled up externally to DVCC during power-up the logical HIGH value might not be read correct by the device (ZERO is read instead of ONE).

Workaround

1) Switch the P1.1/P1.2 Port to logical ZERO after power cycle by:
    a) Switch critical GPIO to output-low (with series resistance to limit current) or
    b) Remove external pull up connection to pull GPIO via internal pull-down

OR

2) Use different GPIOs (not P1.1 & P1.2)

OR

3) Change the polarity of the logical check in SW (enable internal pull-up resistor for the GPIO and pull the external pin to DVSS)