SLOU560 July   2022 TAS2781

 

  1.   Abstract
  2.   Trademarks
  3. 1Description
  4. 2Specifications
    1. 2.1 Power Supply Configurations
  5. 3Device Configuration
    1. 3.1 Jumper Settings
    2. 3.2 Test Points
  6. 4Software
    1. 4.1 PPC3 Overview
    2. 4.2 Device Control Panel
    3. 4.3 Register Map
    4. 4.4 Direct I2C
  7. 5Mono Setup Quick Start
  8. 6Digital Audio Interfaces
  9. 7EVM Schematics
  10. 8Schematic and Layout Guidelines
  11. 9Bill of Materials

8 Schematic and Layout Guidelines

This section provides a list of important items to consider during component selection as well as layout. Following these guidelines help for proper device performance and operation.

  1. All supply rails should be bypassed by low-ESR ceramic capacitors. Consider capacitance derating due to DC as this is considerably critical for higher power rails, a good rule of thumb is to select capacitors with rated voltage 2 or 3 times the supply rail voltage.
    GUID-22000E5B-101B-4C94-AFD5-4A19A9F9BDB3-low.jpgFigure 8-1 Supply Rails Layout
  2. Use GND planes with multiple conductive epoxy filled vias to create a low impedance connection to PGND and GND, this also helps to minimize the GND noise. The layout design must target minimum parasitic loop inductance between PVDDH, PGND pins and decoupling capacitor.
    GUID-137F0DE8-DB01-4626-A572-1682FDF2843C-low.jpgFigure 8-2 GND Layout
  3. Use wider traces that carry high current such as PVDDH, PVDDL, OUT_P and OUT_N.
  4. Connect VSNS_P and VSNS_N as close as possible to the speaker.
  5. VSNS_P and VSNS_N should be connected between the EMI ferrite filter and the speaker if EMI ferrites are used at the outputs.
  6. VSNS_P and VSNS_N routing should be separated and shielded from switching signals such as interface signals, speaker outputs and bootstrap pins.
  7. Place bootstrap capacitors as close as possible to the BSTP/N pins.
    GUID-9007FFC7-665B-4135-9660-3046DBCB7821-low.jpgFigure 8-3 Bootstrap and Outputs Layout