SLPA018 October 2021 JFE150

2 Theory of Operation

The JFET pre-amp circuit is easiest to analyze using the small-signal T-model as shown in Figure 2-1. To understand the operation of this circuit, begin by examining it at the input. A sensor generates a small-signal input voltage (v_in), which modulates the gate-to-source voltage (v_gs) of the JFET. The JFE150 is the first gain stage in the pre-amp circuit and conducts a small-signal drain-to-source current, i_ds = g_m × v_gs which fluctuates with v_in. The small signal current i_ds, is not to be confused with the DC bias current, I_DS = 2 mA, as shown in Figure 1-1. The transconductance gain parameter (g_m), is expressed in Siemens and v_gs is expressed in volts.

Figure 2-1 Pre-Amp With JFE150 Front End Small Signal T-Model

Combined with resistor R₁, the OPA202 forms a transimpedance amplifier that converts the current g_m × v_gs to a voltage, v_out. The OPA202 drives the loop to keep its input terminals approximately equal. As a result, most of the current g_m × v_gs flows through resistor R₁ in the mid-band frequencies, producing an amplified voltage at v_out. Equation 1 calculates the feedforward gain (A_v):

Equation 1.

A_{V} = g_{m} (\frac{m A}{V}) \times R_{1} (Ω)

Convert g_m from decibels to Siemens (mA/V) or Ω^–1, as shown in Equation 2, using the simulated measurement from Figure 2-2.

Equation 2.

g_{m} = {10^}^{(\frac{- 36.08 d B}{20 d B})} = 15.7 m s

Figure 2-2 g_m (dB) vs Frequency (Hz)

Equation 3 and Equation 4 show that the feedforward gain is:

Equation 3.

A_{V} = 15.7 m s \times 1 M Ω = 15.7 \frac{k V}{V}

Equation 4.

A_{d B} = 83.92 d B

Because wafer process variations can yield up to 30% variations in g_m, adding a feedback network (β) maintains a predictable closed-loop gain. The β feedback network consists of resistors R_F2, R_S1, and R_S2 and capacitor C_S, and is a series-shunt feedback network. The β network samples v_out by shunting the output of the OPA202 and feeds back a proportional voltage v_fb in series with v_gs. The source node of the JFET is the feedback-summing node of the circuit. In this configuration, the loop is closed. If v_out rises, then v_fb rises. An increase of v_fb at the source node decreases v_gs, resulting in a reduction of current g_m × v_gs that flows through transimpedance resistor R₁. The final outcome is a reduction of v_out which completes the negative feedback loop of the pre-amplifier. The standard closed-loop gain (A_cl) Equation 5 applies.

Equation 5.

A_{c l} = \frac{A}{1 + A β}

Assuming the feed forward gain A is much greater than β, A_cl is approximately determined by resistors R_F2 and R_S2 in the mid-band frequencies. At frequency, C_S becomes a short and A_cl can be approximately calculated using Equation 6.

Equation 6.

A_{c l} \approx \frac{1}{β} \approx \frac{R_{F 2}}{R_{S 2}} + 1

Equation 7.

A_{c l} \approx 1001 \frac{V}{V} or 60 d B

Figure 2-3 shows the closed-loop gain vs frequency response of the JFET pre-amplifier circuit.

Figure 2-3 A_cl (dB) vs Frequency (Hz)

The loop parameters A, and 1/β can be determined in simulation by breaking the loop. This is accomplished in a SPICE simulator by driving the loop with V_Loop as shown in Figure 2-4.

Figure 2-4 Loop Analysis for Pre-Amp With JFE150 Front End Using the Small-Signal T-Model

At high frequencies the inductor L₁ is an open and the capacitor C₂ is a short. This method isolates the circuits A and β, to plot the frequency response of each, as shown in Figure 2-5. The simulated feedforward gain A is 83.6 dB and closely matches the calculation from Equation 4. The upper –3 dB point of A_cl occurs when A and 1/β meet.

Figure 2-5 Loop Parameters (dB) vs Frequency (Hz)

The low-frequency corners $f_{1} - f_{4}$ are straightforward to determine and are shown in Figure 2-5, Figure 2-3, and Table 2-1. Frequency $f_{1}$ determines the transfer function between v_in and the gate. Components R_G and C_G form a high-pass filter and the –3 dB point of this transfer function occurs at 15.9 mHz.

Table 2-1 RC Combinations and Corner Frequencies

RC Combinations	Corner Frequencies
$f_{1} = \frac{1}{2 π \times R_{G} \times C_{G}}$	15.9 mHz
$f_{2} = \frac{1}{2 π \times R_{S 1} \times C_{S 1}}$	568.4 mHz
$f_{3} = \frac{1}{2 π \times R_{D} \times C_{D}}$	3.98 Hz (See curve A in Figure 2-5)
$f_{4} = \frac{1}{2 π \times R_{S 2} \times C_{S 1}}$	15.92 Hz

Breaking the loop also allows the designer to check for circuit stability as shown with the loop gain (A × β) phase plot in Figure 2-6. The phase margin of this circuit is determined by starting the analysis when the phase of A × β is –180°. Figure 2-6 show that this occurs at $f = 3.98 Hz .$ The reason for starting at –180° is because C_D does not contribute to the phase margin. Capacitor C_D adds a 90° shift from the starting point of the analysis and is a high-pass filter zero. This can be seen in simulation by varying the value of C_D from 10 µF to 5 F or through tedious hand calculations. The phase margin = 267.4 – 180 = 87.4°.

Figure 2-6 Stability Analysis